70% of re-spin issues are AMS in nature: How mixed-signal design can mess up a perfectly good SoC

The title for this blog entry comes from a statement made early in a presentation on SoC design given at this week’s International SoC Conference in Newport Beach, California. The speaker was Cormac O’Sullivan from the S3 Group in Cork, Ireland. O’Sullivan is the RF and Mixed Signal Engineering Team Lead and S3 is a design house specializing in RF and mixed-signal SoC design. The official title of his presentation was “RF SoC Design Flow.”

Why worry about RF and mixed-signal SoC design? O’Sullivan cited figures indicating that more than 80% of SoCs designed today have more than 20% analog/mixed-signal (AMS) content, which is way beyond what you might expect from the usual omnipresent AMS blocks such as PLLs and USB drivers. O’Sullivan also expects that the amount of AMS content on SoCs will zoom up substantially in the next three years. There’s no getting away from on-chip AMS, said O’Sullivan, “ICs need to touch and feel their surroundings.” Increasingly efficient digital signal processing can reduce on-chip AMS requirements but they cannot eliminate them.

However, it’s not the AMS content level in SoCs that catches the imagination. It’s the next statistic O’Sullivan cited. He claims that 70% of SoC re-spin issues are related to AMS design and manufacturing problems.

As long as there are AMS blocks on an SoC—and there always will be—they will disproportionately influence chip yield and respins and they will adversely affect schedules. In addition, AMS IP blocks do not scale well with node shrinks, so SoC designers are always dealing with sub-optimal analog block designs. “In the analog world,” said O’Sullivan, “[AMS] IP always needs to be redesigned for power, function, etc.”

Currently, said O’Sullivan, mixed-signal analog and RF designers speak a different language and use different simulation and verification environments than do digital SoC designers. These differences make communication and common understanding of design intent a real challenge among these two types of hardware designers. Note that this is an issue that Cadence is directly addressing with its recently announced approach to Silicon Realization.

At this point in his presentation, O’Sullivan precisely stated one of the problems Cadence is addressing with a holistic, end-to-end Silicon Realization design flow and connected design from System Realization to SoC Realization to Silicon Realization: communications among different tools and among the different designers working on an SoC design need to be brought together so there’s less chance of misunderstanding and less loss of design intent as the SoC design passes from one stage to the next. “Currently, there are significant problems in the variance in tools used for each [design] phase—lack of coherence results in communication difficulties between system architect and block designers and between block designers and test engineers,” said O’Sullivan.

The S3 Group felt compelled to develop a proprietary system design flow to overcome these issues. The company uses accelerated, cascaded system analysis leveraging Verilog-A for AMS design. For AMS IP block design, S3 Group employs schematic templates and template-driven testbenches and the company uses formal system and block specifications to automatically drive simulations. The company has also automated documentation generation. As a result, S3 Group says it can generate new IP block designs in hours.

“However,” said O’Sullivan, “we can’t simulate these AMS designs at the Spice level” because Spice is too slow and the designs typically won’t converge. Consequently, functional verification is very important in S3 Group’s AMS design flow. The company uses analog functional models in digital simulation environments to speed simulation and to bring different types of designers together. The design flow employs Verilog-AMS wreal values for this purpose, with very tangible benefits said O’Sullivan. An RF transceiver simulation might take 24 hours using Spice—“if all you want is a dc simulation” quipped O’Sullivan. It takes only an hour using Verilog-AMS and wreal.

Finally, O’Sullivan had some advice for serious mixed-signal SoC designs. He suggested that design teams start with multichip designs and a SiP (System in Package) approach until sales volumes can justify a redesign into a monolithic AMS SoC. When sales volumes justify the jump to a monolithic design, much of the original design effort can be reused, significantly reducing the NRE cost and minimizing the time required to make the conversion while keeping overall design risk as low as possible though the entire product life cycle.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in EDA360, IP, Silicon Realization, SoC Realization. Bookmark the permalink.

6 Responses to 70% of re-spin issues are AMS in nature: How mixed-signal design can mess up a perfectly good SoC

  1. Jonathan says:

    Steve, thanks for Statistics indicating that the Mixed-Signal Design Verification specialist is going to be a requirement for most SoC design teams!
    Jonathan

  2. Michael says:

    Wonder if you or O’Sullivan has ever seen an ADC made from digital logic and no analog block. It seems like this new company in Arizona has one for audio bandwidths.
    http://www.stellamar.com

    • sleibson2 says:

      EDN’s analog editor writes: “The scheme uses an LVDS (low-voltage- differential-signaling) input as a comparator.” You can’t perform an A/D conversion without at least a comparator, to my knowledge. I have to admit that using an LDVS differential pair input as a comparator is a great scheme. If you choose to say that’s not an analog block, so be it. I would not say that. As for being “audio” bandwidth, it would be generous to call this A/D design a “voice-bandwidth” A/D converter and it’s not billed as anything but an instrumentation/medical/industrial converter block on your Web site due to the relatively low conversion rate and low resolution. Still, I’m sure it’s a useful design for many applications. Next time, you might want to explicitly identify yourself as the COO of the company you highlight. Just makes things look more on the up and up.

  3. Once again thanks for blogging about my talk and putting S3 Group up in lights!
    Complements on your blog – very interesting insights…
    I look forward to seeing more on Cadence’s holistic design flow.

    I think you captured the essence of what I was trying to say pretty well – although I was trying to be a bit more positive:
    RF/AMS can mess up your perfectly good SoC, if you’re not careful and don’t leverage proven IP and a systematic and proven flow…which S3 Group can provide or can come from in-house experience.

    Also (and hopefully I said this right on the day) the figures I have are ~50% re-spin issues are AMS related but ~70% of yield issues on SoCs are AMS related!

    Thanks again!

  4. Hi Steve,

    Once again thanks for blogging on my talk at the SoC conference and for putting S3 Group up in lights! Complements on your blog – some very interesting insights.
    I look forward to seeing more on Cadence’s holistic design flow.

    I think you captured the essence of what I was trying to say pretty well – although I was trying to be a bit more positive:
    RF/AMS can mess up your perfectly good SoC, if you’re not careful and don’t leverage proven IP starting points and a systematic and proven design flow. (Which S3 group can provide or can be developed in house through experience.)

    Also (and hopefully I said this right on the day) the figures I have are ~50% re-spin issues are AMS related but ~70% of yield issues on SoCs are AMS related!

  5. Given that all electronics is really analog and most digital designers seem to live in a state of denial about that (and a lot of EDA folks in the digital synthesis/verification tools business), 70% is hardly surprising.

    Having worked on Verilog-AMS from its inception at OVI, I can say that for most of the time Cadence have not really helped make it work properly. To be fair neither have Synopsys or Mentor Graphics.

    Marketing spiel would have more weight if it was matched by a similar effort to commit to the standards efforts, and fix the outstanding issues.

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