Are IP subsystems the next big IP category?

Anyone who believes that IP can’t be a profitable business is clearly living in the past century. Take a look at the major IP players in processors, memory, and verification IP (VIP) and you’ll see that there’s “gold in them thar hills.” The reason there’s money there is because IP has simply become an essential part of nanometer SoC design and is an essential resource multiplier that permits SoC design teams to spend resources on product differentiation rather than wheel reinvention. For example, no design team is building its own processors any more. That would be crazy. It’s not that it’s so hard to design a 32-bit RISC processor, a good grad-student design team can whomp one up in a long weekend. Nope, designing a processor isn’t the hurdle; supporting it is. Creating the software-development tools—compiler, assembler, linker, loader, debugger, etc—is one hurdle; Keeping the tools current is another; supporting their use in real designs is yet another. There’s clearly an IP business there.

IP blocks have been getting bigger as well. The first 32-bit RISC processors required only a few thousand gates. Now they sport branch-prediction modules, out-of-order execution engines, and floating-point units, which grow their size considerably.

Late last year, Semico published a report, “IP Subsystems: The Next IP Market Paradigm,” which attempts to create an IP hierarchy based on design teams’ growing reliance on IP for SoC development. It’s an interesting perspective, and with the author’s (Semico Senior Analyst Rich Wawrzyniak) permission, I’m going to write about some of the aspects of the report this week. (If you want more detail, Rich doesn’t mind if you go ahead and purchase the Semico report.)

Wawrzniak posits that the next step up from a simple IP block is the IP Megablock, which he defines as containing more than one type of IP, providing “a higher level of system functionality.” Into this category, he drops processors combined with audio and video codecs such as those available from ARC (now acquired by Virage, which became part of Synopsys)—although other vendors such as Tensilica and CEVA also offer such bundled IP Megablocks.

This IP Megablock concept closely parallels the idea of IP stacks espoused in the EDA360 vision document. Silicon IP alone has far less value than the same IP bundled with appropriate drivers, application software, and expert support.

“However, Semico believes that [the] IP market and IP product development will not the IP Megablock, but will continue to become a full-fledged IP Subsystem,” writes Wawrzniak.

What’s an IP subsystem? It’s a system-level block that supplies major capabilities to the rest of the SoC. Wawrzniak predicts that at least seven such IP Subsystems are imminent:

  • Computing Subsystem
  • Memory Subsystem
  • Video Subsystem
  • Communications Subsystem
  • Multi Media Subsystem
  • Security Subsystem
  • System Management Resource Subsystem

Subsequent blogs this week will explore these ideas further.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in EDA360, SoC Realization, System Realization. Bookmark the permalink.

One Response to Are IP subsystems the next big IP category?

  1. baba12 says:

    I love what you write about. FOr a long time now I have just observed. Thanks for enlightening me with every post.

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