Last month, memory leader Samsung (with more than 40% of the DRAM market according to iSuppli http://www.evertiq.com/news/18960) introduced a new 1Gbit, wide I/O DRAM that uses microbumps to connect its 512 data I/O lines. This design isn’t going to be wirebonded. It’s strictly designed for 3D assembly. (See “Samsung DRAM combines 3D TSVs and wide I/O to move 12.8 Gbytes/sec. Is this the 3D revolution?”.) Yesterday, Hynix Semiconductor (with another 22% of the DRAM market according to iSuppli) announced that it has joined Sematech’s 3D Interconnect program at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, NY. The announced intent of this move is to drive the adoption of wide I/O DRAM. OK, now we’ve got a 3D trend.
Mobile handsets are already the trailblazers in 3D IC assembly. Unfortunately, almost all of that assembly today employs stacked die and wirebonds in a package. When you jump from 32 I/O pins to 512, suddenly wirebonds don’t look so attractive any more. However, wide I/O DRAMs are attractive because they boost transfer rate while cutting transfer clock frequency. You get more memory bandwidth with lower I/O power and that combination is a powerful aphrodisiac for handset makers.
So what do you think? Are you smelling a trend too?