Cadence and TSMC collaborate on SoC IP development, produce complete USB IP package

Working together with TSMC under the TSMC Open Innovation Platform initiative, Cadence has just introduced a certified USB 2.0/3.0 PHY/PCS/controller design IP package to support the wildly popular, advanced USB interface ports for ongoing SoC development using advanced process nodes. TSMC has contributed some “seed IP” to the collaborative effort and the final package was developed and will be marketed by Cadence. (Note that Cadence already offered verification IP for USB 2.0 and 3.0 prior to this latest announcement.)

 

Questions? You’ll find Cadence and TSMC booths side by side at DAC.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in EDA360, IP, SoC Realization, TSMC and tagged . Bookmark the permalink.

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