Today’s the first day of DAC and Cadence is sponsoring a 20nm development panel and lunch at the Omni Hotel adjacent to the San Diego Convention Center. At the same time, Cadence and TSMC have been cooperating on the TSMC Reference Flow 12.0 and Analog-Mixed-Signal (AMS) Reference Flow v2.0 for leading-but-no-longer-bleeding-edge 28nm process technology.
The collaboration included work in electronic system level (ESL), 3D-IC implementation, DFM, and analog mixed-signal (AMS) design. It also includes new technology developed by Cadence and imec to automate production testing of 3D stacked ICs and through-silicon vias (TSVs). (Imec is a micro- and nanoelectronics research center located in Leuven, Belgium.) This new 3D-IC technology extends conventional 2D-IC DFT methods to support dedicated 3D DFT architectures with pre-bond die testing, modular post-bond die and TSV-based interconnect testing, and final testing after packaging.
All of these advanced technologies are required to advance Silicon Realization.
