How many engineers does it take to spin a chip?

The title of this blog entry paraphrases a very old joke category about light bulbs but the topic is serious because it goes to the heart of the electronic industry’s profitability. EDA analyst and ur chip-design guru Gary Smith discussed this topic as part of his Monday morning DAC Trends talk, a DAC staple for many years. After noting that some semiconductor design teams employ 100 to 200 engineers, Smith then asked the question “How many is enough?”

Smith is ultra qualified to ask this question because he’s watch the industry’s developments since before the earliest days of ASIC design and he rides shotgun on the ITRS pricing chart for semiconductor design. Smith’s answer is that you can afford to have no more than 30 hardware engineers working on a chip design. Not hundreds.

Where did Smith get that number? It’s based on the baked-in assumption that competitive chips must cost no more than $25 million to design and that figure includes both the hardware design and the software development. In other words, that’s $12.5 million for hardware design and $12.5 million for software development. No more. When the cost numbers get bigger, design starts fall off. First, the fables companies can no longer afford to design chips and then the IDMs can’t ante in.

How do you get there? Well, IP reuse is one way. Increased tool automation is the other. You cannot afford to throw bodies at IC designs because all you’ll get is increased development cost.

Then Smith went even further with some shockingly simple metrics:

  1. How many hardware blocks on a chip? Answer: five is the ideal. To meet this ideal, design teams will need to fully embrace hierarchical design. “This is a major driver of design productivity,” said Smith.
  2. How large can a block get? Answer: 4 million gates. Beyond this, the tools will choke, your team will spin its wheels trying to unclog the tools, and you will miss deadline and cost targets.
  3. How many engineers per block? Answer: six hardware engineers and six associated verification engineers. How did Smith arrive at that number? 30 hardware engineers divided by five blocks in a chip design equals 6 hardware engineers per block.
  4. How many gates should one tool handle? Answer: 4 million gates (see metric #2). Ideally, a whole-chip EDA tool must handle 20 million gates for an average, high-density chip or 44 million gates to handle a big chip in 22nm.

Increased use of EDA automation is the only way to approach these metrics and Smith sees that we have a long way to go before we get to the automation levels demanded by developments in semiconductor manufacturing capacity and density. Smith concluded, “To be number 1 you must lead in technology, not follow.” His talk points the way. Are you game to take this path?

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in DAC, EDA360, Firmware, Silicon Realization, SoC Realization, System Realization and tagged . Bookmark the permalink.

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