Cadence sponsored a lunchtime discussion panel on 20nm design today at DAC. Veteran industry analyst Jim Handy moderated the panel and the panelists included Simon Segars, Executive Vice President and General Manager for Physical IP from ARM; Ana Hunter, Vice President of Foundry Services for Samsung; Philippe Magarshack Vice President for Design Automation and Libraries for STMicroelectronics; and Chi-Ping Hsu, Senior Vice President, Silicon Realization for Cadence.
Perhaps a 20nm discussion might seem a little esoteric to you. After all, we’re just putting 32/28nm processes in place. This afternoon’s panel in the Omni Hotel ballroom was standing-room-only so a lot of people at DAC would appear to be pretty interested in the topic. The atmosphere didn’t seem one bit rarefied.
Jim Handy started by noting that 20nm was going to be a pretty difficult process node to bring up, mentioning the need for double-patterning as just one of the complicating factors. He then tossed the issue to the panelists, asking what the one biggest obstacle was in each panelist’s opinion.
Segars said that the most difficult issue for 20nm was one of economics. He said we can assume that all of the technical issues will eventually be worked out, as they always have been. That leaves us with the high NRE cost of a 20nm design, said Segars. The question is, will the additional scaling you get over 32/28nm provide enough of an economic benefit to justify the higher NRE costs?
Hunter agreed with Segars about economics being an issue for the 20nm node but she noted that Samsung’s customers were already asking for access to 20nm processing “sooner rather than later.” They must be seeing an economic benefit to make such demands. To provide that access, she said, there is a lot of process and EDA design-flow work still to be done.
Magarshack echoed his other panelists about the technical and cost challenges, but he said that there are a lot of candidate semiconductor products in consumer, wireless, and PC applications with predicted sales volumes that justify the use of 20nm design despite the higher NRE costs. “We need to stabilize the design rules and get going,” he said.
Hsu noted that EDA companies were already starting to make the investment in 20nm tool development. He said that EDA companies together had spent approximately $650 million to develop 65nm tools over time and that the investment for developing 20nm tools are expected to be approximately $1.6 billion. That means the EDA companies are going to need a lot of 20nm tool users to recoup that investment level.
Here are the summations from each of the panelists:
Segars: We will ultimately get there. The question is when and will we have something useful when we arrive?
Hunter: We are already getting close. Samsung is seeing good performance from 20nm transistors produced from lab runs. Meanwhile, she noted, Samsung just announced today that it had qualified its 28nm low-power process and the 20nm process node builds on the successes in developing 32/28nm processes.
Magarshack: We need to abstract the details of the physical process design even more so that designers can focus more attention on architectural details.
Hsu: As long as the processes and the libraries from the fabs work, the EDA tool vendors will make the tools work at 20nm. There are already 20nm test chips coming in from different partners.
So there you have it. Early runs of 20nm wafers are already taking place. The train’s coming. Will you be ready to board?
For Richard Goering’s take on the 20nm panel at DAC, click here.