Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu

Intel announced in early May that it would be using “Tri-Gate” FETs to build microprocessors at the 22nm node. (See the previous EDA360 Insider post “3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D”). Intel’s Tri-Gate transistor structures closely resemble what the rest of the semiconductor industry calls “FinFETs” and I was fascinated by the topic while listening to a crystal-clear talk about FinFETs given last Friday at Cadence’s Building 10 auditorium by Chenming Hu, TSMC Distinguished Chair Professor of Microelectronics at University of California at Berkeley. Hu coined the term FinFET ten years ago when he and his team built the first FinFETs and described them in a 1999 IEDM paper. FinFETs combat short-channel leakage effects that are poisoning bulk planar FET (aka “the good old MOSFET”) performance in advanced-process technology nodes—which is why they’re getting so much attention right now—but there is a competitor to FinFETs called UTBSOI (Ultra Thin Body Silicon on Insulator). Hu’s team developed the first UTBSOI FETs under the same 1996 DARPA contract that funded the first FinFET developments. For more of the story, read on.

This wasn’t Hu’s first FinFET talk at Cadence. He spoke about the topic two years ago but at that time it was an unknown technology he said. Intel’s Tri-Gate announcement six weeks ago raised the new FET technology from obscurity and placed it on center stage. Intel is moving to the 3D gate structure of Tri-Gate FETs because good old MOSFETs are becoming harder and harder to scale now that we’ve achieved double-digit nanometer geometries.

It’s not that we can’t scale the FETs at these smallest process nodes, said Hu. We can, but there are just too many compromises. For example, Ioff (the off current) is too large. Vt, the FET threshold voltage, varies too much across a chip due to small variations in the gate length (Lg) and because dopant levels vary from transistor to transistor across a chip. When geometries as small, all you get are a handful of dopant atoms per transistor so even one dopant atom more or less creates parametric variations. The only way to overcome this variation is overdesign. Combating all of these problems increases design costs and forces Silicon Realization teams to run their designs with higher Vdd (to compensate for Vt variation), which drives up power consumption.

Perhaps the biggest problem is that the MOSFET becomes more and more like a resistor than a switch as gate lengths shrink. At small geometries, the FET drain competes with the gate to control the channel barrier so the gate becomes a much less effective control element. This effect is an exponential function of channel length, so it gets much worse, much faster as we continue to follow Moore’s Law. The classic fix to this problem for many years has been to make the gate oxide thinner and thinner to improve the gate’s electrostatic coupling to the FET channel. Eventually, the conventional silicon oxide barrier used for decades got so thin (measured in a mere handful of atomic layers) that we were forced to use High-K dielectrics to buy back some oxide thickness.

But as the channel length continues to shrink, there’s not much more to be done by fiddling with the gate insulator. Even if we could invent the perfect oxide barrier that was infinitely thin with the “perfect” dielectric constant, it would not be enough said Hu. That’s because the poison runs deep under the channel surface. It’s not up close to the gate. The problem’s in the silicon deeper in the channel. That’s the silicon that’s physically closer to the drain than the gate. There’s a lot of that relatively deep, leaky silicon when the channel is short, said Hu, and the only way to cure the leakage current is to make that silicon disappear.

That was the cure that DARPA sought way back in 1996 when it issued a call for proposals to combat this foreseeable problem. Under that contract, Hu’s team developed two approaches to combating short-channel leakage. The first was the FinFET, which uses a 3D gate structure to make’s the FET gate much more effective by wrapping it around three sides of the channel instead of just one side. To do this, the FinFET’s channel is actually a raised structure—a fin. It no longer sits within the plane of the IC substrate.

The second way to trim the excess silicon from the channel is to fabricate the channel using an ultra-thin layer of silicon that sits on top of an insulator. Hu’s team built that structure too, under the same 1996 DARPA contract, and dubbed it UTBSOI (Ultra Thin Body Silcon on Insulator). The UTBSOI MOSFET simply has no deep silicon for the drain to affect. It’s been eliminated by using the thin silicon film to build the channel.

 

However, to build this sort of FET, you need a way to fabricate SOI wafers with a very thin layer of silicon on top and that thin layer must have a very consistent thickness. “To within 0.5nm” said Hu.

Because the same team built both candidates for future FETs, Hu is able to speak about the advantages and disadvantages of each in a pretty objective way. For FinFETs, it turns out that the most important feature is the fin thickness, which needs to be smaller than or equal to the gate length. Transistor scaling no longer depends on oxide thickness, which is a very good thing because it’s the process lithography than now defines the FET characteristics at each new process node.

Further, said Hu, it only takes one extra mask to create the silicon fin. The FinFET manufacturing process is entirely compatible with contemporary advanced CMOS manufacturing and production techniques. No new magic required. After the fin is constructed, the rest of the processing is essentially planar because the fin just isn’t that tall. Fin height is on the order of 30nm for a fin that’s 20nm thick. After that, said Hu, it’s easy to scale the FETs. Just make the fin thinner and everything else just sort of falls out.

How thin can the FinFET fins get? Hu noted that a university team at KAIST (Korea Advanced Institute of Science and Technology) successfully built 3nm FinFETs using e-beam lithography five years ago in 2006. (I actually wrote about this achievement in the preface to chapter 15 of my book “Designing SOCs with Configured Cores” back in 2006.) However, making one such FinFET is a far cry from production noted Hu. Even so, Hu predicted that Intel would be able to push its Tri-Gate technology below 10nm.

Tomorrow, EDA360 Insider will conclude the discussion of Professor Chenming Hu’s FinFet talk at Cadence with more details about UTBSOI.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
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3 Responses to Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu

  1. Jean-Pierre Colinge says:

    The first “FinFET” was published by Hitachi in 1989 (D. Hisamoto, T. Kaga, Y. Kawamoto, E. Takeda: A fully depleted leanchannel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET. Technical Digest of IEDM, pp. 833-836 (1989)). The first “trigate FET” was invented by the UCL in 1995 (X. Baie, J.P. Colinge, V. Bayot, E. Grivei: Quantum-wire effects in thin and narrow SOI MOSFETs. Proceedings IEEE International SOI Conference, pp. 66-67 (1995) and J.P. Colinge, X. Baie, V. Bayot, E. Grivei: A silicon-on-insulator quantum wire. Solid-State Electronics Vol. 39, pp. 49-51 (1996)). Berkeley and Intel did not invent these devices; they invented their current names (FinFET an Trigate).

  2. Adele Hars says:

    As one can see in Fig.1 of the original ’99 IEDM paper you site, when Chenming Hu and his team invented the FinFET, it was on SOI. A major reason to do FinFETs was to avoid random effects caused by doping. You avoid the doping if you do FinFETs on SOI, was the thinking.

    Industry guru Jerry Fossum explained it very succinctly for ASN back in 2007 (see http://www.advancedsubstratenews.com/2007/05/a-perspective-on-multi-gate-mosfets/ ): “Most importantly, the underlying BOX effectively suppresses the source-drain leakage current under the gated fin-body. Bulk Si would require heavy doping to suppress this current, as well as to effect reasonable device isolation. But one of our goals with MuGFETs is to get away from doping and the random effects it causes: the only pragmatic way to do that is to put the UTB FinFET on SOI.”

    EETimes just published a short piece on a new IMEC comparison of FinFETs on bulk and SOI — IMEC benchmarks FinFET superiority: with undoped SOI FinFETs (SOIFF) power supply can be lowered by another 200-mV EET see http://bit.ly/mKncqd.

    So there is clearly still an argument to be made for putting FinFETs on SOI (for FinFETs, it’s “regular” SOI, by the way — not ultra-thin) — cost savings from ease of manufacturing also still being given as a major reason. (See SOI Consortium study, Nov. 09 at http://bit.ly/lECXrQ). But because Intel’s doing their Tri-gate on bulk, many in the industry are equating FinFETs with bulk. But in fact, FinFETs were SOI first — and (for those not doing planar UTB SOI), they may still be.

    Can’t wait to see tomorrow’s blog on UTB SOI. But I’d also be interested to know if Chenming Hu has addressed SOIFFs at all. If so, do you think you might talk about the possibility of FinFETs on SOI in a future blog, too?

  3. sleibson2 says:

    Jean-Pierre: I did not mean to attribute invention where it didn’t take place. I do note that the team working on the 1999 IEDM paper included people from Hitachi but the paper doesn’t reference the prior Hitachi paper you cite.

    Adele: It’s true that the 1999 IEDM paper from Professor Hu’s team used an underlying insulating oxide to electrically isolate the fin. However, that doesn’t seem to be entirely necessary based on my understanding of Professor Hu’s talk where he showed images of silicon fins without the BOX isolation. As you say, Intel is using a bulk substrate to minimize costs. Bulk seems to work for them. In a similar manner, the 1999 work used e-beam lithogaphy to achieve a gate length on the order of 50nm where that sort of litho isn’t needed for 22nm processing now. In any case, I think the biggest value in Professor Hu’s discussion for me was an understanding of the tradeoffs between FinFETs and UTBSOI.

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