3D Thursday: More words on the Intel FinFETs (this time from Ron Wilson at EETimes)

Last month, I wrote a couple of articles on FinFETs, those 3D structures coming to some 20nm chips soon to be near you—like in your PC. See “Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu (Part 1)” and “Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu (Part 2)”. ) This week, it’s Ron Wilson’s turn to take a crack at the topic. Ron is a good friend who has been writing about electronics technology for a long, long time and has the perspective needed to separate the wheat from the chaff. He’s just published a good article on the EETimes Web site that’s well worth reading about the challenges of nanometer design that are forcing the issue on FinFETs and other ways of building FETs that can operate at these small geometries without incurring disastrous short-channel effects.

As Wilson writes, “The problem is that shortening the channel plays havoc with those other factors—about a dozen different havocs, actually, that get lumped under the label of short-channel effect. Most of these we can summarize by a generalization: as the drain gets closer to the source, it gets harder and harder for the gate to pinch off the channel current. The result is sub-threshold leakage current.

This battle against leakage current has been going on since at least the 90 nm node. The point of the whole high-k/metal-gate (HKMG) transition was to give the gate more control over the channel current without letting gate leakage get out of control. But by the 22 nm node, many are arguing, the planar MOSFET will have lost that war. There will be no way to deliver adequate leakage control at adequate performance. ‘With HKMG we addressed gate leakage,’ one expert said. ‘Now we have to address channel leakage.’”

What’s the solution? One solution is FinFETs. Wilson writes “The finFET gives circuit designers a V-I curve they’ve only been able to dream about since 130 nm.” However, as in all engineering, no solution arrives problem-free. There are liabilities to this approach. Wilson again: “There will be issues for chip designers as well. The fin width will be the minimum process dimension. In order to form the fins, a double-patterning lithography technique—probably spacer-defined—will be mandatory. Double-patterning, in turn, will impose very restrictive design rules.”

Wilson  then proceeds to discuss two more alternatives to FinFETs in the short-channel derby including fully depleted silicon on insulator (FDSOI). So if you’d like even more perspective on these issues, please be sure to take a look at Ron’s article:

“The next transistor: planar, fins, and SoI at 22nm”


You can also see “3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in 3D, EDA360, Silicon Realization and tagged , , , , . Bookmark the permalink.

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