3D Thursday: “For” and “against” arguments for 3D assembly to combat memory bottlenecks

For an excellent discussion about the state of the art in 3D design, click on over to Ann Steffora Mutschler’s article on Chip Design Magazine’s System-Level Design Community (Solving Memory Subsystem Bottlenecks in 3D Stacks). The article discusses several key aspects of 3D design with memory including Wide I/O and cost issues that argue both for and against 3D assembly. Essentially, performance, power, and volumetric space requirements drive the “for” arguments. Reliability, cost, and assembly-process maturity issues drive the “against” arguments. Get a quick read from this article.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in 3D, EDA360, Silicon Realization, System Realization. Bookmark the permalink.

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