Who else wants to see a 60x speedup in DFM signoff on a 28nm design?

Rambus has announced that it achieved a 60x speedup in DRC for an IP design targeting a 28nm process technology using GLOBALFOUNDRIES’ DRC+ methodology. This approach to DRC is interesting because it’s the industry’s first approach to DRC that teams silicon-validated libraries of yield-critical patterns with automatic pattern classification and pattern matching. Technically, these procedures are beyond DRC and well into DFM, which is why GLOBALFOUNDRIES calls it DRC+. Lithographic DFM checks became mandatory at 45nm to address lithography issues, etch effects, and systematic manufacturing variations that now dominate over random variation in limiting IC production yield. Manufacturing shapes on an exposure mask interact with optical proximity halos and other characteristics of lithographic projection systems to create highly nonlinear (hard to predict using models alone) variation.

Rules-based DRC approaches cannot accurately predict these effects because they fail to identify many potential yield issues that produce opens (necking) and shorts (bridging) on a 28nm die. Boosting production yield requires the detection and repair of these pattern-induced failure modes before tapeout. GLOBALFOUNDRIES’ approach to solving this problem at 28nm is to create silicon-validated libraries of yield-critical patterns—certified bad patterns already known to fail in 28nm manufacturing. A 2D, shape-based pattern-classification technology supplied by Cadence then classifies patterns likely to fail using these libraries and brings these patterns to the designers’ attention earlier in the design process. GLOBALFOUNDRIES and Cadence announced  a collaborative effort on this technology a year ago but the work goes back much farther than that.

This approach to DFM delivers significant speed improvements for detecting and correcting layout errors. In the Rambus case, the noted speedup was as much as 60x compared to “traditional methods.” Further, this approach “essentially eliminated any significant issues at signoff” according to Keith Windmiller, senior director of Design Technology at Rambus. One of the many nice things about this technology is that it scales almost linearly with the number of CPUs you throw at the problem.

If you would like to find out more about this technology, head over to the Global Technology Conference  being held at the Santa Clara Convention Center on August 31, 2011. There’s a Cadence presentation at 4:40 on unified analog/mixed-signal and digital design flows that incorporate this advanced DFM approach.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in EDA360, Globalfoundries, Silicon Realization and tagged , , , , , . Bookmark the permalink.

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