On Tuesday, October 25, you will learn how Texas Instruments and Cadence goosed the ARM Cortex-A15 processor core into the GHz+ range using an end-to-end digital design flow that includes physical-aware logic synthesis, DFT, timing optimization, optimized CTS (clock-tree synthesis), and routing. However, it takes a few tricks to get that high in the clock-rate stratosphere, so be prepared to hear about a few tricks. Want the tips?
Check out the session description:
“Flow and tools, tips and tricks: Implementing successful Cortex-A15-based designs”
And then register for ARM TechCon 2011 here.
