Ambarella cuts power on HD camera controller SoC using Samsung 32nm process technology

Last month, I wrote about the introduction of Ambarella’s new A7L SoC for controlling HD video and digital still cameras. (See “3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors”.) That blog entry discussed how Ambarella took its design from a 45nm process technology to a 32nm process technology and bumped the on-chip ARM 1136K-S RISC processor from 528MHz to 600MHz. At the time, I speculated that the real driving concern here was power consumption. Today’s announcement by Ambarella, Cadence, and Samsung (Ambarella’s foundry for the A7L SoC) confirms that conjecture.

According to Chan Lee, VP of VLSI at Ambarella, ““Impressively, Samsung Foundry’s process technology, combined with the Cadence digital flow, enabled us to hit our aggressive performance targets while achieving 95 percent power savings during power shutoff mode and 60 percent average power savings over operation and sleep modes.”

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in ARM, EDA360, Low Power, Samsung, Silicon Realization, SoC, SoC Realization and tagged , , , . Bookmark the permalink.

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