Power, Performance, Cost. FDSOI lets you pick any three. Want proof? How about an ARM Cortex-M0 processor core example?

Last week, the first session of the International SoC Conference focused on FDSOI (fully depleted silicon-on-insulator) IC fabrication. Now if your thinking resembles mine before I watched this presentation, you think that FDSOI is an advanced IC-fabrication process that gives you better performance at lower operating power—and at a cost that’s higher than for bulk CMOS designs. Not so said IBM’s Gorden Starkey, who was speaking for the SOI Industry Consortium. You are to be forgiven for thinking that SOI costs more. The underlying wafer does indeed cost more. “But,” said Starkey, “FDSOI takes a step backwards to move forwards.” By that, he meant that there are now so many implants made during bulk CMOS circuit fabrication that the costs for making ICs with bulk CMOS are actually higher than for making IC based on FDSOI. In fact, said Starkey, the reduced complexity of manufacturing ICs using FDSOI is about 10% less than for bulk CMOS because FDSOI-based manufacturing saves some 25 implant steps.

So FDSOI offers electrical benefits (faster transistors, lower power consumption) and fabrication-cost savings. Even further, geometric lithographic shrinks increasingly favor FDSOI.

So how about some proof? Coming right up. Starkey discussed a 20Kgate, 20nm test vehicle based on the ARM Cortex-M0 processor core. He then projected this slide showing Fmax plotted against total power at Fmax:

Here’s how to read this graph. The bottom curve plots Fmax versus power consumption at various operating voltage levels for 20nm bulk CMOS using a low-power process technology. The top curve plots Fmax versus power consumption at various operating voltage levels for 20nm FDSOI. At any point on the lower curve, you can find out the Fmax for a given operating voltage, and then move horizontally to the left to see what the power consumption is for the FDSOI version of the design at the same operating frequency.

For example, the bulk CMOS version of the ARM Cortex-M0 processor core with a 1V supply voltage dissipates just over 130mW while operating at roughly 220MHz. (Note: The ARM M0 has a 3-stage pipeline, which limits the maximum clock frequency.) Looking at the upper curve, you see that the FDSOI version of the ARM Cortex-M0 processor core delivers the same 220 MHz at a 0.9V supply voltage while consuming a bit less than 100mW. That’s already a substantial power savings (about 23%).

However, you can also make use of FDSOI’s back-bias abilities to also cut down on leakage current, which is what the straight line passing through the 0.9V operating point in the FDSOI curve. The back-bias adjustment allows you to dynamically set the operating point of the processor core, with greatly reduced leakage (a 10x reduction) or improved performance (260MHz) depending on the back bias.

Remember, you save 10% of the fabrication cost while getting these improved performance and power-consumption numbers.

Significantly, said Starkey, there are no particular difficulties with existing EDA tools to design FDSOI circuits. There are modeling changes needed for transistor-level simulations, but these models are now becoming available (and were the subject of the presentation immediately before Starkey’s).

About these ads

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in 20nm, ARM, Cortex-M0, FDSOI, Silicon Realization, SoC, SoC Realization and tagged , , , , . Bookmark the permalink.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s