3D Thursday: Hybrid Memory Cube—Does anyone know what’s happening with IBM and Micron?

Perhaps all will become clear next week at IEDM being held in Washington, DC

This week, IBM and Micron apparently made a joint announcement (or perhaps just IBM made an announcement) regarding the manufacture of Micron’s Hybrid Memory Cube. There are varying reports and I cannot find the original statements on either company’s Web site. A ZDNet article by Larry Dignan is titled “IBM to make Micron’s Hybrid Memory Cube with its 3D chipmaking process” while a CNET article by Brooke Crothers is titled “Micron to tap IBM chip-stacking tech for fast memory.”

ZDNet’s Dignan writes:

“Micron will begin production for the first chip to use through-silicon vias (TSVs), IBM’s 3D chip making process. The TSV process will be used in Micron’s Hybrid Memory Cube. Parts for the Micron’s chip will be manufactured at IBM’s chip fab in East Fishkill, N.Y.”

Well, the Hybrid Memory Cube will not be the first chip to use TSVs. But let’s just ignore that bit of incorrect hyperbole.

There are two major components in the Hybrid Memory Cube: memory die and a logic die. From the above text, it’s not clear which company will be making what. Both Micron and IBM are members of the Hybrid Memory Consortium, which was started and announced by Micron and Samsung in October. (See “3D Thursday: Hybrid Memory Cube—wide I/O only more so—gets an industry consortium”)

CNET’s Crothers writes:

“IBM’s technology is based on something called through-silicon via, or TSV: vertical conduits that electrically connect a stack of individual chips. Because of the ability to stack chips, TSV is sometimes referred to as 3D. This technology will be combined with Micron’s state-of-the-art DRAM.”

That TSV description is slightly wrong. 3D assembly is more than TSVs, although TSVs are mighty helpful in 3D IC assembly. However, the statement does seem to say that it’s Micron’s DRAMs that will be used in the Hybrid Memory cube stack.

Crothers also writes:

“IBM will manufacture its Hybrid Memory Cube components at its semiconductor plant in East Fishkill, N.Y., using the company’s 32-nanometer high-K metal gate process technology.”

Now the Hybrid Memory Cube stacks a number of SDRAM die on top of a logic die, so Crothers statements make me believe that IBM will be fabricating the logic die while Micron fabricates the SDRAM die for the Hybrid Memory Cube. Then one or both companies will assemble the Hybrid Memory Cubes for their own purposes—IBM perhaps for internal use and Micron for commercial sale.

Perhaps all will become clear at next week’s International Electron Devices Meeting (IEDM) http://www.his.com/~iedm/ being held in Washington, DC. That’s where IBM will be discussing its TSV technology.

Note: The Hybrid Memory Cube is a very interesting attempt to break through the memory wall, which is an increasingly troublesome problem and performance limiter for processor-based design, especially multicore SoC design. For more information on the hybrid Memory Cube and its potential to break through the “memory wall,” see “Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?” and “3D Thursday: Micron’s 3D Hybrid Memory Cube delivers more DRAM bandwidth at lower power and in a smaller form factor using TSVs

Note: After writing this blog entry, I found Mark LaPedus’ article about the topic, which seems to confirm the assumptions I made made above.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in EDA360, Low Power, Memory, SoC, SoC Realization, System Realization, TSV and tagged , , , . Bookmark the permalink.

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