DARPA wants a more PERFECT processing engine with a 75x improvement in GFLOPS/Watt. Want to play?

Further proof that power consumption now rules the design envelope is the announcement of DARPA-BAA-12-24 calling for an increase in embedded computing power efficiency from approximately 1 GFLOPS/W to 75 GFLOPS/W. If you think all of that efficiency improvement is going to come from Moore’s Law scaling, you’ve not been paying attention for the last decade. Fortunately, DARPA has been paying attention. As the DARPA document says:

“In the past, computing systems could rely on increasing computing performance with each processor generation. Following Moore’s Law, double the number of transistors was available with each processor generation. And according to Dennard’s Scaling, clock speed could increase 40% each generation without increasing power density. This allowed for increasing performance without the penalty of increased power. However, this free ride in processing performance increases is over. Increasing clock speeds would now result in unacceptably large power increases. As transistor operating voltages approach the logic threshold voltage, the device operating characteristics change dramatically: reliability and maximum operating frequency both decrease. Industry has only a limited ability to reduce operating voltage to avoid these clock frequency decreases, since reliability and operating frequency are critical to their user base. These factors have led to limitations on improvements in commercial processing power efficiency.

The goal of the Power Efficiency Revolution For Embedded Computing Technologies (PERFECT) program is to provide a power efficiency of 75 GFLOPS/w for embedded computing systems. The PERFECT program will achieve this goal by taking a revolutionary approach to processing power efficiency. This approach includes near threshold voltage operation and massive heterogeneous processing concurrency, combined with techniques to effectively utilize the resulting concurrency and tolerate the resulting increased rate of soft errors. The PERFECT program will leverage and incorporate anticipated industry fabrication geometry advances to 7 nm. Since no operational hardware is to be built in this program, a simulation capability will be developed to measure and demonstrate progress.

This program specifically addresses embedded systems processing power efficiencies and performance, and is not concerned with developments that focus on exascale processing issues.”

This is a 5-year project that starts this year.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in EDA360, Low Power and tagged , , , . Bookmark the permalink.

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