Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP

In conjunction with this week’s Ethernet Technology Summit being held in San Jose, Cadence has announced commercial availability of MAC (Media Access Control), PCS (Physical Coding Sublayer) and BEAN (Backplane Ethernet Auto-Negotiation) IP blocks. The 40/100G MAC controller is fully compliant with the IEEE 802.3ba-2010 standard for Ethernet interfaces running faster than 10Gbps. The MAC IP block has separate, 128-bit paths for transmit and receive FIFOs and a separate configuration interface. It supports a wide variety of Ethernet features including support for IEEE 802.1AS for precise timing and synchronization, 802.1 priority queuing for audio/visual bridging, and 802.3az Energy Efficient Ethernet. On the PHY side, the Cadence 40/100G Ethernet MAC supports both the 40G PCS media independent interface called XLGMII and the 100G PCS media independent interface called CGMII.

The two PCS blocks implement the 40G and 100G physical coding layers respectively. The coding layers are the digital part of the Ethernet PHY and the Ethernet standards permit the formal separation of the PCS and SerDes to support multiple transmission media. The 40GBASE-R PCS block interfaces to four transmit and four receive 10G SerDes modules through eight separate, unidirectional 16/32-bit interfaces (four interfaces in each direction). The 100GBASE-R PCS block can interface with either ten 10G Ethernet SerDes blocks in each direction or four 25G SerDes interfaces in each direction.

The BEAN IP block implements the IEEE 802.3ap Clause 73 auto-negotiation function through the use of independent hardware state machines. Here is a block diagram showing how these four Ethernet 40/100G IP blocks relate to each other:

These IP blocks have already been licensed and taped out for high-volume production. Deliverables include the Verilog HDL code for the block, synthesis scripts for the Cadence Encounter RTL Compiler, a Verilog testbench, and documentation.

For Richard Goering’s take on 40/100G Ethernet, see his new blog post: “Who Needs 40/100 Gigabit Ethernet SoCs?

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
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