Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development EDA tools in connection with SoC Development. I know there are a lot of skeptics out there, and I do not blame you. It is easy to be skeptical when a marketing cat starts talking tools. However, everyone knows Schirrmeister deals from the top of the deck, which is why I found his talk so credible. He dealt with real problems and solutions available to help solve those problems.
So here it is in a nutshell. Here’s a typical waterfall diagram of chip development:
If you’re and experienced member of an SoC Realization team, there’s absolutely nothing strange about this diagram. Now your numbers may vary from this diagram but the diagram’s numbers are normalized averages over a dozen SoC design projects. For the past three decades, EDA companies have focused on squeezing this development cycle for ASICs.
However, we’re no longer in the ASIC era. We’re in the SoC era.
What’s the difference? As they said in the movie “The Graduate,” one word: software. There is a huge amount of effort and a lot of expense missing from this diagram that goes into developing the software that must be developed to make the SoC do anything useful.
Starting in 1995, chip-development teams started to add processor cores to the ASIC component mix, thus creating SoCs. At first, it was a big deal to just add one processor. Then two—perhaps one general-purpose processor and one DSP. Then four. Then many—as in many cores. All of these cores need software to run. Otherwise, you have laid down a lot of useless transistors on your chip.
Now we have a development cycle that includes a significant amount of software development. The new development cycle looks like this:
Note that we now need to develop OS support, software utilities, and the software applications (apps in EDA360 parlance) that will add the desired capabilities to this chip. Look carefully and you’ll see the huge development overhang that application software development places on the overall project schedule.
We as an industry are now working on ways to reduce that development overhang and we are attacking this problem with a variety of tools.
Here’s the image Schirrmeister showed for those tools:
Briefly the four tools are Virtual Prototyping, faster RTL simulation and verification, Emulation Acceleration, and FPGA-Based Prototyping. All of the major EDA vendors are working on tools that perform these four functions.
Virtual prototypes permit early software development by creating fast software system models that can run actual code through transaction-level modeling (TLM). RTL simulation and verification are familiar tasks to all SoC Realization teams who simply need to perform these tasks faster and with less hassle as they move from transaction-level models to RTL descriptions. Emulation accelerators take this need for speed up another few notches. FPGA-based prototypes can get operational hardware into the hands of software developers faster so that the coding can go faster. (Not coincidentally, these four types of system-development EDA tools are the four components of the Cadence System Development Suite.)
All of these tools have one overarching objective: reduce the software-development overhang that’s now hampering Soc Realization.
I hope to have a video of Schirrmeister’s presentation available soon. Stay tuned to the EDA360 Insider.