Scaling the 20nm peaks to look at the 14nm cliff, Part 1: Tom Beckley from Cadence maps the challenges of advanced node design at ISQED

Yesterday at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote that lays out the challenges for IC designers tackling advanced node designs at 20nm and below. The room at ISQED was filled with a couple of hundred people and did they ever get an earful. Beckley’s team of 800 EDA developers has been working closely with customers to get the kinks out of 20nm design and has also started down the path to 14nm. Lessons learned from these early 20nm designs fueled Beckley’s talk, titled “Taming the Challenges of Advanced-Node Design.”

Normally, I’d summarize the talk for you here in the EDA360 Insider but Beckley’s presentation really doesn’t need my help at all. His message is already as clear as a finely cast bell so I’m replicating his talk here in detail. There’s so much information in this presentation that I’ll be splitting it into two parts. Part 1, describing the challenges of 20nm design, begins here:

Taming the Challenges of Advanced-Node Design

Cadence has been on a 20nm journey for more than a couple of years, working closely with industry-leading foundries and multiple customer partners. As a result of working with these partners on several early 20nm test-chip designs, we’ve learned more than a few things about 20nm design. One of the things we’ve learned is how the nature of the chip-design team is going to change.

There are interesting perceptions regarding the analog and custom design community. Terms like “black art”, “whiz kids” or more likely “prima donnas” are often used, but there is no doubt that circuit designers are key to enabling SoCs to interface to the real world.

Why? Because humans are fundamentally analog.

Custom CAD layout engineers have always lived in the world of getting GDSII out the door as quickly as possible while ensuring layouts can be manufactured with high yields. They live in a world of high pressure, where everything is matched, symmetrical, and ordered.

Some years back, it was not uncommon for there to be a wall between circuit designers and layout engineers. At 65nm and below, especially in the world of custom digital and high performance analog, we’ve seen those walls tumble as physical effects—especially parasitic effects—have an increased impact on circuit design specifications.

The impact of 20nm design on the relationship between the circuit designer and the CAD engineer is significant. Indeed, circuit designers must become more involved with their digital RTL counterparts at 20nm and below.

I recently spent two days with a large design team doing a 20nm USB PHY post-design review. They learned many lessons during this project but two were very clear:

  1. Circuit designers must now be very aware of complex physical effects … more and more mandatory verification runs are extending design time
  2. Physical complexity has exploded. Instead of needing two or three designers per layout engineer, the team needed three or four layout engineers per designer. We will delve into why this is the case. Net/net – they’d never experienced a design challenge so severe.

Compared to designs at the 28nm process node, the 20nm node potentially provides upwards of 20% better performance, a 30% power savings, and a 50% area reduction (100% increase in transistor density). As a consequence, we will see upwards of 30B transistors on a 20nm SoC.

Three significant challenges at 20nm

Semiconductor/EDA enablement will help satisfy these trends at 20nm and 14nm. But we face three significant challenges.

First there’s the massive investment cost associated with the 20nm node. Here is a chart showing some of the costs involved:

Development and manufacturing at 20nm and below is painfully expensive. Fab costs at 20nm practically double. This is also true across process, design, and mask costs. As a consequence, SoC designs at 20nm must have the right mix of features, functionality, and performance to achieve the volumes needed to achieve ROI goals. Consumer applications for mobility—and the infrastructure that enables mobility—will be the key high-volume designs that can amortize the big investment in 20nm. As you can see from the above chart, the break-even number could be as high as 60 to 100 million units.

EDA companies are heavily re-tooling for 20nm and below, and this work requires close collaboration with foundries, equipment suppliers and customers. The EDA industry as a whole spends $1.5 to $2 billion a year in R&D. Most of our EDA R&D is spent addressing new challenges such as those presented by new processing nodes. Any process node generally lasts 4-6 years per node. Of the 800 people in my organization, almost half spend the majority of their time on advanced node development.

The second major challenge presented by the 20nm node revolves around manufacturing complexity, which quickly moves upstream into design complexity. At some process nodes, the shift in complexity has been less pronounced—as in going from 45 to 28nm. The 20nm process node marks a distinct shift in complexity. The following chart shows the design and manufacturing challenges associated with the 20nm node.

Why is 20nm a seismic shift?  Because of new devices, a multitude of very difficult and competing design rules, advanced lithography effects, and the need to design differently. 20nm transistors are small and very fast. Routing and source/drain parasitics dominate. Consequently, physical complexity explodes and circuit parasitics and mis-match in the analog realm become so severe that designers will use more digital control circuitry and calibration where analog design alone used to be sufficient. The hope is that the seismic shift at 20nm will take us through 14nm and possibly 10nm.

The third challenge is integrating more and more functionality in such a way that time-to-market targets can be achieved. The massive real estate available at 20nm means more IP from different parties will be integrated, more complex packaging will be required, and given that mobility is key—low power is the most important characteristic of all.

Scaling analog and RF circuitry at advanced nodes is a major challenge. Placing this circuitry near large noisy digital compounds the challenge. These circuits have many power modes with transition time requirements. Verification times are massive. Reliability, overstress, aging and current limits add to the tons of simulations that must be managed. Therefore, alternative methods for creating systems including TSVs (through silicon vias) and stacked-die approaches are being simultaneously prepared.

Let’s take a more in-depth look at the 20nm challenge from a custom IC design perspective including the impact on designers and CAD engineers.

Double Patterning

The resolution of a photoresist pattern begins to blur around 45nm even with the use of phase-shift masks, which were introduced for the 180nm node when feature size dropped below the wavelength of the 193nm light being used for lithographic exposures. Double patterning was first introduced for the 32nm node to attack this problem, but was generally avoided to the extent possible for cost reasons. However, it is very difficult to avoid double patterning at the 20nm node even when using state-of-the-art 193nm immersion lithography equipment.

Double patterning splits the design layers into two separate masks for structures that are too close together to expose properly with just one mask. At 20nm, we just can’t achieve the trace pitch we want with just one mask.

Each of the two layer masks used for double patterning is separately exposed to produce one resulting image in the photoresist. Clearly, double patterning is more expensive in terms of increased mask costs and it presents unique challenges from a design perspective, especially in custom design where complex devices and interconnect designs must minimize parasitics and mismatch while maximizing performance.

Double patterning brings a “coloring” challenge to design. Coloring algorithms first appeared to help produce 180nm phase masks but these algorithms—in much more advanced form—are now used to generate the two layer masks for double patterning.

Double patterning creates its own challenges. In the simple example below, you can see that one can very quickly create something that is design-rule correct, but can’t be manufactured.

You might think that a simple “flipping of the color” would resolve the problem, but merely flipping the color results in a design-rule violation. This problem can ripple across the entire design fairly quickly, so intelligence is required in the design tools to handle these complexities.

To no one’s surprise, a host of issues aggressively manifest at 20nm.

Second- and third-order parasitics become important at 20nm

Analog circuit designers have always been concerned about minimizing parasitics for interconnect and devices. Parasitic capacitance, resistance, and inductance are handled with detailed test benches that analyze multiple corners to ensure the circuit will function as specified despite parasitics.

While these parasitic issues have always been present at larger nodes, they were second- or third-order effects that could be designed around. At 20nm, things aren’t so forgiving and many of these effects must now be “pre-analyzed” and accounted for during the design phase. You can’t just fix them later. You won’t have the time. You must prevent them from occurring in the first place.

Layout-dependent effects include accounting for traditional device and wire effects and the effects of devices and wires related to their surrounding environments. Here’s a chart that shows six layout-dependent effect you can expect to see at advanced nodes and how large the effects become at 20nm and below.

Anywhere from 20-30% of a circuit’s performance can be attributed to the effects of the surrounding environment. Foundries expect customers to go through a whole set of new verification steps to detect these effects so that they are fixed before the GDSII file is sent for manufacturing. These effects cannot be dealt with in PCell device models, device callbacks, and estimated wire-load models.

Two such layout-dependent effects are shallow-trench isolation (STI) and the well-proximity effect (WPE). Shallow trench isolation for a device must take into account the distance from the edge of a gate to each diffusion edge, gate-to-gate separation, and the overall length of the diffusion. Any hand crafting of devices or groups of devices including any folding, merging, abutting, and dummy insertion all incur STI effects and consequently affect device performance.

Therefore, circuit designers must estimate the impact of these complex parasitics earlier in the design flow to quickly detect potential problems. Physical engineers will find themselves drawn into the circuit designer’s simulation flow to ensure parasitic closure. However, physical engineers will not have the time to deal with complex parasitic effects because they have a whole host of new challenges of their own to manage.

Many more design rules—more than 400 new ones

We’ve grown accustomed to an increased number of design rules at each new node but for 20nm it really is a brave new world. There are more than 400 new complex physical design rules when going from 28nm to 20nm—far too many rules to memorize.

Beyond more complex parasitic challenges and a host of new physical design rules, there are new interconnect layers. Foundries will require use of new Local Interconnect (LI) layers, also called Middle-of-Line layers (MOL), for 20nm designs.  These new “in-between” layers will be used to create densely packed routes inside complex devices. These new local interconnect layers have their own set of restricted design rules governing local interconnect and the vias used with them. This new interconnect wrinkle at 20nm presents significant challenges to maintain signal integrity from one transistor pin to the next.

So, how are we addressing these 20nm challenges making design more manageable and end product more successful? Come back to the EDA360 Insider tomorrow for Part 2 of Tom Beckley’s compelling presentation.

(Note: For another look at the challenges of 20nm design, see “Want to know what’s going to happen at 20nm, 14nm, and beyond? A few answers from Frank Leu of Cadence”)

For Richard Goering’s take on Tom Beckley’s keynote, see “ISQED Keynote: 20nm From a Custom/Analog Perspective

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in 14nm, 20nm, EDA360, Silicon Realization, SoC, SoC Realization and tagged , , , . Bookmark the permalink.

One Response to Scaling the 20nm peaks to look at the 14nm cliff, Part 1: Tom Beckley from Cadence maps the challenges of advanced node design at ISQED

  1. karthik s says:

    nice intro abt the challenges to be faced

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