Freescale demonstrates first-pass Kinetis L silicon at Design West (The conference formerly known as the Embedded Systems Conference)

Two weeks ago, ARM introduced its new low-end Cortex-M0+ 32-bit processor core. At the same time, Freescale announced that it was planning on introducing a new line of Kinetis “L” low-power microcontrollers based on the ARM Cortex-M0+ processor. (See “How low can you go? ARM does the limbo with Cortex-M0+ processor core. Tiny. Ultra-low-power.”) Today at Design West (The conference formerly known as the Embedded Systems Conference, ESC) I saw working first-pass silicon for the first member of the Kinetis L microcontroller family, I got a demo of the working silicon at the Freescale booth, and I attended an hour-long presentation on the ARM Cortex-M0+ processor core and the Kinetis L microcontroller family.

Here’s a photo of the demo:

The first-pass Kinetis L microcontroller silicon is installed in a board in the Freescale Kinetis Tower system. There are two towers with identical Kinetis L microcontrollers but running slightly different code to demonstrate the superiority of one new ARM Cortex-M0+ feature: single-cycle fast I/O. This feature specifically targets designers using 8- and 16-bit microcontrollers who still want to bang bits (and anyone else who wants low-latency I/O). You can’t really bang bits through a buffered bus controller and the ARM Cortex-M0+ processor core achieves 33% to 100% faster I/O than through other sorts of bus schemes for earlier ARM Cortex-M cores. That’s one of the take-aways I got from Eduardo Montañez, a Freescale Systems Engineer who gave me the demo.

The second major feature is the Micro Trace Buffer, a 1.5Kgate piece of on-chip hardware that captures changes in program flow and stores this information in on-chip RAM. There are some real advantages to this hardware-debugging approach. First, the Micro Trace hardware stores just enough information so that the debugger can reconstruct the program trace. This sparse trace information packs neatly away in a little bit of on-chip RAM. Next, this small amount of data downloads quickly through the microcontroller’s serial debug port into a debugging pod. Finally, the on-chip RAM used to capture the trace data can be reclaimed and used for data storage when you’re no longer debugging the software. It’s a very slick way of providing you with vastly improved debugging capabilities using a minimum of on-chip resources.

The third major Kinetis L microcontroller feature is the memory controller that Freescale uses to link the ARM Cortex-M0+ processor core to the on-chip NAND Flash memory. The controller has a 64-byte RAM buffer that helps to significantly reduce the number of NAND Flash access cycles. In turn, the reduced number of accesses to NAND flash boosts performance when running directly from NAND Flash memory and reduces operating power by exercising the NAND Flash memory less frequently.

During a subsequent presentation on the Freescale Kinetis L family at Design West later in the day, there was much discussion about the plans for using the ARM Cortex-M0+ processor core to supplant 8- and 16-bit processors. There are several reasons why some 8- and 16-bit microcontroller design teams want to migrate to 32 bits. These reasons include:

  • You can really only get performance from 8- and 16-bit processors by using assembly code (as opposed to C or C++) and there are fewer and fewer such assembly coders each year. In addition, assembly code is not portable the way that programs written in C are portable.
  • 8- and 16-bit processors have relatively crude debugging facilities.
  • Advanced communications stacks (think Ethernet, Bluetooth, USB, etc.) are much easier to implement with 32-bit processors.
  • 8- and 16-bit processors are generally not designed using ASIC-like design methodologies so they adapt to new process nodes with some amount of difficulty. There’s also a question about how long these architectures will last. Freescale, a major 8-bit microcontroller vendor itself, says that these processors are nearing the end of their useful life.
  • 8- and 16-bit processors have limited address spaces, frequently augmented with block-switching schemes that complicate the creation of quality, portable software.
  • Many complex, intelligent peripherals (think Ethernet, PCIe, USB, advanced memory controllers, etc.) are only or largely available for 32-bit processors.

Note: There are still advocates of 8-bit and 16-bit processors out there. I apologize in advance if these six points upset or offend you, however I am not making these points. Freescale is. And Freescale still sells 8- and 16-bit processors.

Code footprint remains one of the main bugaboos in considering the adoption of 32-bit processors in markets currently using 8- and 16-bit microcontrollers. Freescale displayed this slide at the Freescale presentation, which shows code footprint in Kbytes for the code needed to implement the CoreMark microprocessor benchmark:

Note that the ARM Cortex-M0+ processor core (and the ARM Cortex-M0 processor core with an identical ISA) requires less code space than the 8- and 16-bit processors it’s being compared to. Does that mean that the ARM Cortex-M0+ always needs less code space than 8- and 16-bit processors? Probably not. It does mean that code space may not be as large an issue for 32-bit processors as you currently think.

Power and energy consumption are also big considerations in the 8- and 16-bit microcontroller realm. Freescale is using a 90nm TFS (thin-film storage) low-power IC process technology to build the Kinetis L microcontrollers, which keeps operating power low. The company could implement its 8- and 16-bit microcontrollers in this technology but because these older designs were not created using ASIC design methodologies, the likelihood of scaling these older designs declines with each new process generation.

Process scaling is one of several strategies Freescale has used to reduce operating power in the Kinetis L microcontroller family. Take a look at this chart from the Freescale presentation:

The chart shows a power-consumption profile over time and compares an older microcontroller’s power profile (shown in red) with that of the Kinetis L microcontroller (shown in green). There are four peaks in this power profile. The first peak shows an initialization phase in the software. The Kinetis L microcontroller consumes less power during this phase for two reasons. First, the more advanced IC process technology cuts the maximum amount of power consumed resulting in a lower peak. Second, the additional computational power of a 32-bit processor architecture results in a narrower peak. Essentially, the 32-bit processor finishes the initialization phase sooner so the microcontroller draws peak power for less time.

The next two peaks show large amounts of power reduction—a result of the use of smart peripherals and an independent, on-chip DMA controller that can move data between peripherals and memory while the processor sleeps. It’s possible to put smart peripherals and a DMA controller on an 8- or 16-bit microcontroller but again, the likelihood of modernizing these older microcontroller designs declines with time.

Once the data is collected, the microcontroller enters the compute phase to process the data. Again, the low-power process technology and the faster computing ability of the 32-bit processor greatly reduce the amount of power used in this phase. The overall power reduction is substantial.

During the presentation, one question arose about the use of 90nm process technology for the Kinetis L microcontroller family. The questioner noted that 90nm was no longer such an advanced IC process node. The reply—an excellent one—was that 90nm is currently the sweet spot for microcontroller manufacture because leakage rises significantly at 65nm and below and because a large part of the microcontroller chip consists of analog and mixed-signal blocks that cannot currently take advantage of smaller process geometries.

Finally, here’s a slide from the presentation showing plans for a large Kinetis microcontroller family from low-end members running at 50MHz (or below)—based on the ARM Cortex-M0+ processor core, and selling for less than 50 cents in quantity—to high-end members based on the ARM Cortex-M4 processor running at hundreds of MHz and sporting large amounts of on-chip memory. One of the key points of this slide is that the ARM Cortex-M processor core family allows companies such as Freescale to create large, software-compatible microcontroller product lines.

And those products are coming, as the first image in this blog post proves.

For some really interesting information describing how Freescale designs the Kinetis microcontroller family members, click here.

Freescale just posted a video of the ARM Cortex-M0+ Kinetis L demo at this week’s Design West. Here it is:

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in 65nm, AMS, ARM, Cortex-M0, EDA360, Firmware, Silicon Realization, SoC, SoC Realization and tagged , , . Bookmark the permalink.

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