I’ve already written many blog entries about the Micron Hybrid Memory Cube (HMC), a 3D stacked memory device that can deliver a theoretical DRAM bandwidth of 128Gbytes/sec to a host system using a 4-die stack of DRAM (NOT SDRAM) on top of a logic die. Several things have happened with the HMC this week of particular note.
First, late-breaking news! Micron will now be presenting more information about the HMC and the HMC Consortium at the Electronic Design Process Symposium being held in Monterey, California on April 5 and 6. Micron will be presenting the morning of Friday, April 6 during what I’ve been calling 3D Friday. You now have less than a week to sign up for this event and if you have any interest in 3D IC assembly, then you need to be in Monterey on April 6.
More information about EDPS here.
Register for EDPS here.
During my conversation with Micron’s Mike Black this week at Design West (the conference formerly known as the Embedded Systems Conference) , I discovered that Micron has indeed built a working HMC prototype assembly. Despite having written many previous blog entries about the HMC, I did not realize or remember that there was an operational prototype, but there is. The prototype HMC delivers 121Gbytes/sec of bandwidth, which is 95% of the target. Not bad for a first prototype. Not bad at all.
Meanwhile, the HMC Consortium is already working with the second-generation specification for the HMC and Micron expects to have sample assemblies ready by the first half of 2013. Black tells me that these initial parts will be based on DRAM die from Micron attached to a logic die made by IBM. Micron will perform the final assembly and packaging of the 3D HMC.
Black noted that some companies may want variations in the design of the logic die—particularly with the interface between the HMC and the host system. Micron will provide a design service to create those logic die variants.
Now would be a good time to mention that Cadence has signed on to the HMC consortium as an Adopter. 3D design requires 3D EDA tools. Hence Cadence’s interest in the HMC.
Additional blog entries about the HMC include:
- 3D Thursday: Micron’s 3D Hybrid Memory Cube delivers more DRAM bandwidth at lower power and in a smaller form factor using TSVs
- Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?
- 3D Thursday: Hybrid Memory Cube—Does anyone know what’s happening with IBM and Micron?
- Is 2012 going to be another breakout year for NAND Flash and Low-Power Design?