What are the challenges of EUV lithography and the issues surrounding double patterning? CDNLive! presentation provides details.

Richard Goering has just published an excellent blog post on double patterning for 20nm and 14nm process geometries in his blog Industry Insights. The post is based on a paper presented by IBM Distinguished Engineer Lars Liebman at the recent CDNLive! Cadence user group meeting held in Silicon Valley. Liebman’s presentation, titled “Quantifying the Design Impact of Double Patterning for the 20nm and 14nm Technology Nodes,” is a detailed study of double patterning using 193nm light sources and 13.5nm EUV (extreme ultraviolet aka soft X-rays).

Goering writes this about EUV lithography:

“Liebmann then offered a detailed look at EUV. Before this presentation, I had not realized how exotic and complex this technology is.”

Twelve years ago in 2000, Keith Diefendorff wrote about EUV lithography extensively in a very detailed Microprocessor Report article titled “Extreme Lithography.” Diefendorff detailed many of the same challenges still being faced today by EUV researchers and placed a timeline in that article showing production tools for EUV lithography being delivered in late 2005. That prediction turned out to be wildly optimistic. Goering’s blog post reports that IBM now expects that date to now be some time in 2013, about eight years later than predicted in Diefendorff’s article.

It’s not that the companies focusing on EUV lithographic development are slow or not paying attention. Far from it. EUV lithography is really, really hard. Even today, the EUV light source is two orders of magnitude dimmer than needed for high-throughput IC making. And that’s only one of five EUV challenges Goering lists in his blog post.

Where does that leave us?

It leaves us with double patterning for 20nm and possibly double or triple patterning with 193nm light for the 14nm node.

Goering’s post then goes on to discuss some really interesting experiments with routability, circuit density, and double patterning—done jointly by IBM and Cadence—detailed in Liebman’s CDNLive! presentation. You’ll find Richard’s blog post with more details about these experiments here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in 14nm, 20nm, Double Patterning, EDA360, EUV, Silicon Realization and tagged , , , , , , . Bookmark the permalink.

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