Want more information on the ARM Cortex-M0+ processor core?

Last week, ARM CPU Product Manager Thomas Ensergueix presented a Webinar on the ARM Cortex-M0+ processor core, which I’ve covered previously over on the Low-PowerDesign.com Web site http://www.low-powerdesign.com. (See “How low can you go? ARM does the limbo with Cortex-M0+ processor core. Tiny. Ultra-low-power.”) The Webinar went through the new processor core in detail and I think you will find may of these details quite interesting.

But first, take a look at this set of curves that Ensergueix included in his presentation:

As you can see, the dollar volume of 32-bit microcontrollers has been climbing pretty steadily for the past decade and a half except for the recent recession, which was a disaster for all microcontrollers. The 8-bit microcontrollers continue to hold their own and probably represent a higher unit sales volume due to lower ASPs while 16-bit microcontrollers have also been on the rise. These curves leave little doubt that 32-bit microcontrollers are now successful—and ARM certainly wants to make them more so, hence the release of the new ARM Cortex-M0+ processor core.

It’s a relatively simple core, as 32-bit processor cores go, with seventeen 32-bit registers (including thirteen general-purpose registers, three special-purpose registers, and a program status register), 56 instructions (50 of these instructions are 16-bit instructions for compact code footprint), a 4Gbyte linear address space, an optional memory protection unit, a nested vector interrupt controller that can initiate an ISR in 15 or 16 clock cycles, a fast 32-bit peripheral I/O port that bypasses much of the bus logic, and a Micro Trace buffer that can store compressed trace information in the microcontroller’s local SRAM (all of this RAM is available to the running code if trace isn’t being used).

Power consumption for the ARM Cortex-M0+ core implemented in 180nm process technology and running at 1.8V core voltage is shown as 42 microamps/MHz.

Processor size is tiny. Here’s a chart showing the size for 180nm, 90nm, and 40nm.

Although the ARM Cortex-M0+ is brand new, Freescale has already announced the development of a new microcontroller line around the processor, the Kinetis L, and demonstrated first silicon (see “Freescale demonstrates first-pass Kinetis L silicon at Design West”). Meanwhile five other microcontroller vendors (Energy Micro, NXP, Nuvoton, ST, and Samsung) have announced microcontrollers based on the code-compatible ARM Cortex-M0 (not Plus) processor core in the sub-$1 price range. I expect even more entrants in this arena based on the ARM Cortex-M0+.

The ARM Cortex-M0+ Webinar is now available on demand. Click here.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in ARM, Cortex-M0, EDA360, Silicon Realization, SoC, SoC Realization and tagged , , , , , , , , . Bookmark the permalink.

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