3D Thursday: A funny thing happened to me on the EDPS 3D-IC panel

Last Friday, I moderated an all-star, hand-picked 3D-IC panel at the Electronic Design Process Symposium (EDPS) in Monterey, California. The panel included:

  • Phil Marcoux, Managing Director, PPM Associates, experienced packaging expert
  • Herb Reiter, President of eda2asic, Chair of the Global Semiconductor Alliance 3D/TSV Working Group, and organizer of the EDPS 3D-IC Friday sessions
  • Samta Bansal, Senior Manager of Product Marketing for SoC Realization, Cadence
  • Dusan Petranovic, Technical Marketing Engineer, Mentor Graphics
  • Steve Smith, Senior Director, 3D-IC strategy and marketing, Synopsys
  • Deepak Sekar, Senior Principal Engineer, Rambus (recently of MonolithIC 3D)

Funny thing is, as moderator I was not able to take any notes during the panel and that was most unfortunate because the panelists covered a lot of interesting ground with respect to 3D IC design and assembly issues. There were even a few surprises, which I didn’t expect based on how much I write about 3D ICs each Thursday.

Fortunately, Richard Goering was in the EDPS audience and took excellent notes, which he’s transformed into an extensive blog post about the panel session titled “What Needs to Happen for 3D-IC TSV Success” in his Industry Insights blog. From my perspective as the panel’s moderator, Richard’s post is 99% complete. He cropped me out of the photo of the panelists; that’s about the only thing missing from his post and it’s truly a minor omission.

You really should check out Richard’s post. I know you’ll find it interesting.

For some additional perspectives, see Francoise von Trapp’s blog post on the event.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization and tagged , , , . Bookmark the permalink.

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