3D Thursday: Qualcomm’s Nick Yu says “3D DRAM stacking has started—it’s shipping in products”

Today’s GSA Silicon Summit held at the Computer History Museum in Mountain View, California included a talk on 3D IC assembly by Nick Yu, VP of Engineering, VLSI Engineering, at Qualcomm. Yu is in charge of Qualcomm’s technology roadmaps including wafer fab process nodes, backend interconnect, and packaging technologies. He opened his talk by discussing the Qualcomm Snapdragon series of mobile application processors (see “Qualcomm renames existing ARM-based Snapdragon mobile application processors and provides future roadmap”). Qualcomm Snapdragon processor chips combine one to four 32-bit RISC processor cores with a GPU, display controller, sound subsystem, and various I/O interfaces. All of these IP blocks go onto one 2D die but Qualcomm can’t afford to stop there. There’s more to a mobile phone handset than an applications processor. You’ll also find chips for RF, memory, power control, and sensors. “We need 3D because all of this is out of the question [in monolithic 2D form],” said Yu.

“And cost drives everything,” he added, making that fact very clear with one slide. The slide showed two curves: GSM mobile handset unit cost over time and GSM mobile handset sales volume over time. “Once we dropped below $200,” said Yu, “worldwide sales really took off” referring to a sharp knee in the sales-volume curve that led to billion-unit annual sales. That’s why we need low-cost 3D IC assembly, continued Yu. “Cost opens the door to sales volume.”

Qualcomm has already worked on 3D IC technology development projects to help prepare the company for a 3D future. “3D DRAM stacking has started—it’s shipping in products because it has maintained the bit density/cost ratio,” said Yu. The next thing that will happen, he predicted, is memory stacked on logic. Here, Yu specifically mentioned Wide I/O and Wide I/O 2 SDRAM, which deliver more memory bandwidth at lower operating power than DDR memory. (See “3D Week: JEDEC Wide I/O Memory spec cleared for use” and “Where does LPDDR3 SDRAM fit in the low-power memory universe? How about Wide I/O SDRAM?”.)

The Holy Grail, said Yu, is full 3D IC assembly that fits RF, memory, power, logic, and sensor die into one package. “It will take a lot of hard work to make this happen,” he predicted. “The thermal envelope is perhaps the biggest limiting factor, but power consumption is another major consideration,” Yu continued, “Batteries aren’t getting better. However, if we don’t make the cost structure right, it’s not going to happen for cellphones.”

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization and tagged , , , , , . Bookmark the permalink.

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