Four Significant EDA technologies of 2011 and what they mean to your IC design team

This week, Cadence celebrated the efforts of several developers who have created some very innovative technology during a private award ceremony. The reason I’m mentioning this internal event at all is because these celebrated technologies are already having a profoundly positive influence on worldwide IC design efforts. I think you’d be interested in four of the highlighted technologies:

The first of these technologies is called FlexColor, a double-patterning-aware routing algorithm with built-in 20nm design-rule checking that produces correct-by-construction mask patterns for dual-pattern 20nm masks. Cadence developed the FlexColor algorithm to pair with the 20nm “good-pattern” libraries being developed by silicon foundries. These libraries are an essential part of 20nm design and are used to create manufacturable ICs at the 20nm node.

FlexColor is used in the Cadence NanoRoute Advanced Digital Router, which routes at both the block and chip levels for 20nm designs as well as for IC designs at the 28nm and 32nm nodes, the mainstream 40nm and 65nm process nodes, and all the way up to the 130nm node—essentially all the process nodes currently in volume production. This is just one example of how advanced EDA research and development for today’s most aggressive IC designs also improves the EDA tools used to develop new designs in more mature—bit still mainstream—IC process nodes.

(Note: Cadence FlexColor technology use was discussed last year at the September Global Technology Conference. See “GTC Presentation: Cadence Outlines Comprehensive 20nm Design Flow” by Richard Goering.)

The second highlighted technology, the Cadence GigaOpt optimization engine, is a fast RTL-to-GDSII optimization engine that delivers optimal PPA (performance, power, and area) and better correlation between front-end design and back-end implementation—in other words, significantly faster design convergence.

(Note: For more information on the Cadence GigaOpt optimization engine, see “The Technology Behind Encounter 11.1 – Optimization for GHz, Giga-Gate, and 20nm Design” by Richard Goering.)

The third highlighted development is the Cadence Virtual System Platform, which allows design teams to use TLM (transaction-level modeling) for early software development. Design teams can save a tremendous amount of development time by starting software development and debugging much earlier—six to nine months before an RTL description is written and many months before the silicon is ready—by using an abstracted model of the hardware. This advantage really speeds up hardware/software integration and represents a substantial competitive advantage for design teams. In some cases, design teams have created working virtual prototypes in days using the Cadence Virtual System Platform.

(Note: For more detailed information on the Cadence Virtual System Platform, see the blog post “Welcome to the Cadence Virtual System Platform” by Jason Andrews.)

The final highlighted innovation is the Cadence VIP Catalog. It’s no secret that verification takes a healthy chunk of the system and SoC development schedule. Validating IP, SoC, subsystem, and system integration are big tasks. The Cadence VIP Catalog eases the time and effort needed for this verification by providing a ready-made VIP catalog—a one-stop shop—with support for:

  • More than 40 protocols including the ARM AMBA interconnect fabrics, PCI and PCIe, Ethernet, USB, HDMI, MIPI, SAS, SATA, and others.
  • More than 6,000 memory device models from 85 manufacturers using a wide range of memory interfaces including DRAM interfaces (including DDR1, DDR2, DDR3, Mobile SDR/DDR, Mobile DDR2, GDDR2, GDDR3, GDDR4, GDDR5), Flash interfaces (including NOR, NAND, OneNAND, ONFi, Perfect NAND, Toggle NAND), and storage media interfaces (including CE-ATA, CompactFlash, SD, eSD (embedded SDCard), Memory Stick, Memory Stick Pro, MMC, and eMMC)

Combined, these VIP offerings cover a very wide range of interfaces that every System and SoC design team must address. The Cadence VIP Catalog supports all major logic simulators, the Universal Verification Methodology (UVM), and common testbench languages such as SystemVerilog and e. In addition, Cadence recently added the TripleCheck IP Validator to the Cadence VIP Catalog, which simplifies and accelerates compliance testing of interface design IP.

(Note: For more information on the Cadence VIP Catalog, see “Cadence Denali Acquisition Results in Broad Verification IP (VIP) Offering” by Richard Goering and this news article: “New Cadence Verification IP Catalog for Silicon, SoC, and System Realization.”)

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in EDA360, Silicon Realization, SoC, TLM, VIP, Virtual Prototyping and tagged , , , , . Bookmark the permalink.

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