Does Soc verification leave you in a cold sweat? Read on…

Do you identify with this scenario:

“I’m the verification lead on the biggest SoC our company has ever done. It’s taping out today and I’ve got that familiar sick feeling in my gut. When will the first undiscovered functional bugs start cropping up?

-In next week’s ongoing simulation runs? Please, let it just be a metal layer fix.

-In the first hour after silicon comes back? Everyone will blame me as if anyone could have caught something so obvious.

-After the lead customer gets first silicon? Please no, I can’t take another beating from my VP.

I’m going down with this chip and there’s nothing I can do about it. I hate my job.”

If that’s you, then you are going to want to read Tom Hackett’s SoC discussion in today’s Tech Talk on ChipEstimate.com. Hackett walks you through verification in a way I’ve never seen: clearly, step-by-step, with answers to your most vexing problems.

His main theme, of course, is the mounting verification problem in the face of SoC complexification. There’s no question that SoCs are more complex than ever. Just start by counting the number of processors on the chip. Where once we worried about gates, we’re now worried about IP blocks or entire IP subsystems (Gary Smith calls them platforms) on chips. As SoCs become more complex, so does the verification task. How could it be otherwise?

So the question is how to get through the verification task faster with better confidence in the results. Read Hackett’s answer here.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in EDA360, SoC, SoC Realization, Verification. Bookmark the permalink.

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