AMD’s new Trinity APU (Accelerated Processing Unit) for laptops/notebooks is a poster child for IP-centric SoC design

Yesterday, AMD introduced its second generation of A-series APUs (Accelerated Processing Units) that combine two to four Piledriver x86 microprocessor cores—each with 2Mbytes of L2 cache memory—with a Radeon 7000 GPU (Graphics Processing Unit), an HD Media Accelerator, a display controller with HDMI port, a dual-channel DDR3 SDRAM controller, and 24 lanes of PCIe interconnect. Here’s a die photo/block diagram of the dual-core version:

AMD markets these APUs under the “Fusion” and “Vision” brands and the AMD press release for the new APU series lists five members: two have two x86 processor cores and three have four processor cores. According to AMD, this sort integration will allow laptop/notebook vendors to build products that sell for as little as $500 with as much as 12 hours of battery life.

From a design perspective, the new A-series AMD APUs illustrate the way SoCs are now being designed. The die photo clearly shows an assembly of IP blocks including the Piledriver x86 processor cores, the associated L2 memory caches, the GPU, HD Media accelerator, DDR3 SDRAM controllers, and the PCIe I/O blocks. Using a calibrated eyeball, these identifiable IP blocks appear to consume more than 80% of the device.

To see the complete AMD slide deck on the announcement, click here.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at http://eda360insider.wordpress.com/)
This entry was posted in 32nm, EDA360, Silicon Realization, SoC, SoC Realization and tagged , , , , , , , . Bookmark the permalink.

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