Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments in favor of Wide I/O SDRAM’s use in mobile devices. Wide I/O SDRAM
- Increases the number of die-to-die interconnect by 10x
- Increases bandwidth by 10x
- Reduces per-connection capacitance by 6x
- Reduces power-per-connection by 6x
You may have already read about Wide I/O SDRAM, but did you know that the adoption of Wide I/O memory also influences DRAM controller design? It does. You can hear all about it in this video, presented by Marc Greenberg at DAC. The information on 3D, Wide I/O, and TSVs starts about 12 minutes and 50 seconds into the video.
