There are three primary reasons why we are seeing more system and semiconductor companies consider 20nm: performance, power, and area (PPA). Essentially, this is a “next-node” answer, which is still as true as ever at 20nm.
What are the specific benefits of 20nm?
- 2x gate density Improvement
- 20% speed improvement at Vdd=0.85V
- 25% switching power reduction
- Multiple Vt and Lg options extends performance coverage
What are the primary design challenges at 20nm?
There are three kinds of challenges:
- Silicon manufacturability and managing variations
- “Giga-scale” design productivity
- Concurrent “performance, power, and area” optimization
Do you really need double-patterning technology (DPT) at 20nm?
Mostly everybody moving to 20nm will need to use it [DPT], because conventional lithography is not cutting it any more.
What kinds of transistor counts can be expected at 20nm?
20nm is expected to provide 8 to 12 billion transistors [per chip], so that’s a huge increase in the size of designs, and it’s done with a 2x density shrink and 50% better performance.
What is new and different at 20nm?
One aspect that gets worse involves layout-dependent effects (LDE). At 20nm, cells are much closer to each other and the proximity effect of different kinds of cells and interconnects has a worse effect on both timing and power.
Note: These questions were adapted from a new Cadence White Paper titled 20 Questions on 20nm. For more in-depth answers and for more questions, see the White Paper.