Category Archives: 20nm

Want to know what’s going to happen at 20nm, 14nm, and beyond? A few answers from Frank Leu of Cadence

Posted on March 19, 2012 by

Last week at the Global Technology Forum held at the Santa Clara Convention Center in Silicon Valley, Cadence VP of R&D Frank Leu discussed the things we’ve learned about 20nm IC manufacturing, what we are learning about 14nm, and where … Continue reading →

Posted in 14nm, 20nm, 28nm, EDA360, Globalfoundries, Samsung, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , | 2 Comments

By the numbers: 20nm (and 40nm, 32nm, 28nm, and 14nm) design to be discussed in technical detail at next week’s CDNLive! conference in Silicon Valley

Posted on March 5, 2012 by

There’s still time to register for CDNLive!, which is being held on March 13 and 14 at the Doubletree Hotel in San Jose, California so let me give you a few numbers to whet your appetite: 40nm, 32nm, 28nm, 20nm, … Continue reading →

Posted in 14nm, 20nm, 28nm, 32nm, 40nm, CDNLive!, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , , , , | Leave a comment

Friday Video: Common Platform Technology Forum reveals program agenda, rolls into Silicon Valley on March 14

Posted on March 2, 2012 by

The Common Platform partners are IBM, Samsung, and GLOBALFOUNDRIES and their annual Technology Forum  rolls into Silicon Valley on March 14, so you have a couple of weeks to sign up. This short video from ChipEstimate.com gives you a good … Continue reading →

Posted in 14nm, 20nm, 28nm | Tagged , , , , , , | Leave a comment

GSA Silicon Summit to highlight cutting-edge IC technologies: 3D IC assembly, FinFETs, and SOI. April 26, Silicon Valley

Posted on February 7, 2012 by

The Global Semiconductor Alliance (GSA) is sponsoring a half-day event that will drill down into three of the leading-edge IC manufacturing technologies of the coming decade: 3D (and 2.5D) IC assembly, FinFETs (or Tri-gate FETs), and silicon-on-insulator (SOI) substrates. The … Continue reading →

Posted in 2.5D, 20nm, 28nm, 32nm, 3D, EDA360, FDSOI, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , | 1 Comment

CDN Live covers the gamut of IC design on March 13 and 14 in San Jose. Register Now.

Posted on January 12, 2012 by

Registration for CDN Live—the 2-day technical conference for Cadence users being held on March 13 and 14 in San Jose—has just gone <er> live. Before I give you the link, I wanted to let you know about some of the … Continue reading →

Posted in 20nm, 28nm, 32nm, CDNLive!, EDA360, Silicon Realization, SoC Realization, System Realization | 1 Comment

What will EDA and chip design look like in the year 2020? Prognostications from the ICCAD panel

Posted on November 8, 2011 by

Last night, half a dozen ICCAD panelists attacked the topic “2020 Vision: What the recent history of EDA will look like in nine years.” That’s such a convoluted and hard-to-parse title that the panelists chose to discuss the state of … Continue reading →

Posted in 20nm, 28nm, 3D, DAC, Design Abstraction, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , | 4 Comments

Power, Performance, Cost. FDSOI lets you pick any three. Want proof? How about an ARM Cortex-M0 processor core example?

Posted on November 7, 2011 by

Last week, the first session of the International SoC Conference focused on FDSOI (fully depleted silicon-on-insulator) IC fabrication. Now if your thinking resembles mine before I watched this presentation, you think that FDSOI is an advanced IC-fabrication process that gives … Continue reading →

Posted in 20nm, ARM, Cortex-M0, FDSOI, Silicon Realization, SoC, SoC Realization | Tagged , , , , | Leave a comment

Where’s the sweet spot for IC process technology right now? Semico has an answer

Posted on October 12, 2011 by

Semico just released its latest wafer demand report for 2011 and the top-line conclusion isn’t wonderful but it’s not horrible either. Unit sales and wafer demand in the electronics industry will be up for the year but falling ASPs mean … Continue reading →

Posted in 20nm, 28nm, 65nm, EDA360, Silicon Realization | Tagged | Leave a comment

Friday Video: What does it take to get to 20nm? Samsung’s VP of Foundry North America Ana Hunter explains

Posted on October 7, 2011 by

Samsung has been pushing IC process technology about as hard as any company in the business. It’s foundry business is operating at 65nm and 32/28nm with a 20nm process node in development. (See my recent blog “Samsung 20nm test chip … Continue reading →

Posted in ARM, EDA360, Silicon Realization, Verification, 20nm | Tagged , , | Leave a comment

Want some more details about the Samsung 20nm test chip? Here’s your chance: ARM TechCon 2011 on October 25

Posted on October 4, 2011 by

Later this month, you have the opportunity of attending the ARM TechCon 2011 conference being held in the Santa Clara Convention Center in California. Tuesday, October 25 is dedicated the many different aspects of advanced to SoC design and the … Continue reading →

Posted in 20nm, ARM, EDA360, Samsung, Silicon Realization, SoC Realization | Tagged , , , | Leave a comment

Here’s more food for thought regarding 20nm design. Do you know what it takes?

Posted on September 13, 2011 by

One week ago, I described some of the 20nm process node benefits and challenges discussed in Wei Lii Tan’s presentation at the recent Global Technology Conference. (See “Just how high is the 20nm design mountain of challenges?”) Now Richard Goering … Continue reading →

Posted in 20nm, Double Patterning, EDA360, Silicon Realization | Leave a comment

Even more on 20nm design and the Cadence talk at GTC from Richard Goering

Posted on September 7, 2011 by

Click on over to Richard Goering’s latest post about the Cadence 20nm presentation made last week at the Global Technology Conference. Goering goes into even greater technical detail that I did in my post on the talk (see “Just how … Continue reading →

Posted in 20nm, EDA360, Silicon Realization | Leave a comment