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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- Nvidia Tegra 3 based on five ARM Cortex-A9 cores is mobile processor of the year declares Microprocessor Report
- Friday Video: Two more low-cost, ARM-based, embedded-Linux development boards from ODROID and Google
- 3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- Collaboration is key to making DFM work at 28nm and below
- Xilinx 28nm low-power SoC design class, part 2: Process Technology
- 3D Thursday: Micron to present Hybrid Memory Cube status at EDPS in Monterey, April 6—there’s a lot of news
- Friday Video: Webcam + Open-source video code + Arduino Uno microcontroller board + pan/tilt servo make automated face-tracker, prove the power of an apps-centric world
- Cavium “Thunders” approval of 64-bit ARM v8 processor cores for cloud and server apps
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Category Archives: Design Intent
Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm
This week at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote covering the industry’s challenges and progress at 20nm and … Continue reading
Posted in 10nm, 14nm, 20nm, 28nm, Design Abstraction, Design Intent, DFM, Double Patterning, EDA360, IBM, Silicon Realization
Tagged 10nm, 14nm, 20nm, 28nm, extraction, FinFET, ISQED, layout, parasitic
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Learn how an analog design flow can boost your IC design productivity…FREE (Breakfast and Lunch too!)
You’ve got just a few days only before the new series of free technical seminars on analog design flows for analog, mixed-signal, and custom designs can boost your team’s design productivity. The key to boosting design productivity is reducing design … Continue reading
Posted in Design Abstraction, Design Convergence, Design Intent, EDA360, Silicon Realization
Tagged Analog, Mixed Signal
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“Welcome to the era of Smart Devices”says Intel’s Gadi Singer. Are you ready for the design competition?
Intel’s Gadi Singer (vice president and general manager of Intel’s SoC Enabling Group) gave the keynote presentation at DAC 2011 yesterday and he discussed the evolution of electronic devices into vehicles that deliver experiences. To do this, these devices must … Continue reading
“Professor” Aart de Geus gives latest Techonomics lecture on collaboration and System Realization at the Semico Summit in Scottsdale
Last week, Synopsys Chairman of the Board and CEO Aart de Geus gave a keynote at the Semico Summit in Scottsdale. His topics were “Techonomics,” collaboration, and systemic complexity. Techonomics is de Geus’ name for the fusion of technology and … Continue reading
Posted in Apps, Design Abstraction, Design Convergence, Design Intent, Ecosystem, EDA360, System Realization
Tagged Aart de Geus, Semico Summit, Synopsys
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What’s driving 3D IC design? Do 2D EDA tools need a total overhaul to support 3D design?
The Electronic Design Process Symposium (EDPS) held last week in Monterey devoted most of Friday to a discussion of 3D design. I’ll be devoting several EDA360 Insider blog entries to this important topic. Today’s entry summarizes the presentation by Rahul … Continue reading
The critical need for expressing design intent within EDA
Mark Waller, VP of Engineering at Pulsic, just published a great article on design constraints on the chipdesignmag.com Web site. (See “It’s Time for Standard Design Constraints for Custom Design”.) Design constraints go by another name in the EDA360 vision, … Continue reading
Posted in Design Intent, EDA360, Silicon Realization
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