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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- Friday Video: Webcam + Open-source video code + Arduino Uno microcontroller board + pan/tilt servo make automated face-tracker, prove the power of an apps-centric world
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- Nvidia Tegra 3 based on five ARM Cortex-A9 cores is mobile processor of the year declares Microprocessor Report
- Raspberry Pi + Canon = Camera Pi: ARM 11 and Linux hack of a Canon 5D Mk II DSLR
- Friday Video: Learn the fundamentals of PCB design in 47 minutes, and enjoy it
- TI Stellaris LaunchPad eval board features ARM Cortex-M4F. Intro price: $4.99. Get yours now.
- Xilinx Zynq EPPs based on two ARM Cortex-A9s create a new category that fits in among SoCs, FPGAs, and microcontrollers
- The other shoe drops: Altera introduces SoC FPGA, mates ARM Cortex-A9 dual-core processor complex with FPGA fabric
- Itching to try out the Xilinx Zynq-7000 EPP? Ask your doctor if Zedboard is right for you
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Category Archives: TLM
DAC 2012: Get answers to all of your EDA questions at 78 Cadence demo suite slots
Next week (Monday, Tuesday, and Wednesday) you can get all of your EDA questions answered at the Cadence DAC demo suites. There are 78 demos over the three days covering the following EDA topics: Mixed-signal and low-power design RTL-to-GDSII design … Continue reading
Posted in DAC, EDA360, Low Power, Mixed Signal, pcb, Silicon Realization, SoC, SoC Realization, System Realization, TLM, Verification, VIP, Virtual Prototyping
Tagged DAC, EDA, IC design, pcb, synthesis, verification
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Four Significant EDA technologies of 2011 and what they mean to your IC design team
This week, Cadence celebrated the efforts of several developers who have created some very innovative technology during a private award ceremony. The reason I’m mentioning this internal event at all is because these celebrated technologies are already having a profoundly … Continue reading
Free Webinar for Verification Engineers on using Structured Debug Messages. March 7.
Structured debug messages (SDMs) help verification engineers perform advanced transaction-level debugging by linking transactions throughout their environment and by linking messages to a specific transaction or to a parent transaction. SDMs also help you to visualize transactions in a debug … Continue reading
Posted in EDA360, System Realization, TLM
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System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang
Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading
IEEE Computer Society Lecture—Creating System-On-Chips: Mixing HW & SW Successfully
As soon as we started to incorporate processors on ASICs, thus instantly creating SoCs, hardware/software integration issues became fully intertwined with chip design. Today, we routinely put a dozen or more firmware-driven processing elements on our SoCs so the issues … Continue reading
Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0
Chocolate and peanut butter go together. So do SystemC and transaction-level modeling. Just not officially. Until now. Earlier this month, the IEEE Standards Board approved a revision to the IEEE 1666 SystemC standard to bring the widely used OSCI (Open … Continue reading
Posted in Design Abstraction, EDA360, SoC Realization, System Realization, SystemC, TLM
Tagged Accellera, EDA, IEEE 1666, OSCI, SoC Realization, SystemC, TLM
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Want to start writing code for the two ARM Cortex-A9 processors on the Xilinx Zynq-7000 EPP right now? Virtual Platform makes it possible
As of today, you can start to develop application software for the Xilinx Zynq-7000 family of Extensible Processing Platforms (EPP) using a virtual prototyping platform announced today and jointly developed by Xilinx and Cadence. The virtual platform provides an accurate … Continue reading
Posted in Apps, ARM, Cortex-A9, EDA360, FPGA prototyping, SoC Realization, System Realization, TLM, Virtual Prototyping
Tagged ARM Cortex-A9, Cadence, Linux, Multi-core processor, SystemC, Xilinx
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Friday Video: All about the TSMC ESL Reference Flow 12
ESL Reference Flow 12 is the latest generation TSMC reference flow for electronic system-level (ESL) design. The TSMC ESL Reference Flow 12 inserts power, performance, and area (PPA) indices into an ESL design flow, which enables designers to explore meaningful … Continue reading
Posted in EDA360, Silicon Realization, SoC Realization, System Realization, TLM
Tagged ESL
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A painless way to learn how to design and debug multicore ARM-based SoCs using SystemC and TLM 2.0
As SoCs become far more software-centric, and multicore SoCs even more so, Realization teams must prototype and debug their designs using virtual platforms before committing to the implementation phase or face the high risk of proceeding down the wrong architectural … Continue reading
Posted in ARM, EDA360, SoC Realization, System Realization, SystemC, TLM, Uncategorized, Virtual Prototyping
Tagged A9, Cortex, M3
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