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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
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- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- Qualcomm renames existing ARM-based Snapdragon mobile application processors and provides future roadmap
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Want a peek at a possible Qualcomm 3D IC roadmap?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Thursday: Wide I/O and TSVs have a ripple effect on the DRAM controller. Who knew?
- Agilent knocks one out of the park with new, low-cost line of digital scopes—a very competitive entry into the low-end DSO market and a perfect example of EDA360 design using end-to-end design and apps.
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
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Category Archives: Wide I/O
3D Thursday: Wide I/O and TSVs have a ripple effect on the DRAM controller. Who knew?
Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading
Posted in 2.5D, 3D, DAC, EDA360, IP, Silicon Realization, SoC, SoC Realization, System Realization, TSV, Wide I/O
Tagged DRAM, JEDEC, Marc Greenberg, Mobile device, SDRAM, Wide I/O
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3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—“Learn to work together”
Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about … Continue reading
Posted in 2.5D, 3D, DAC, EDA360, Low Power, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O
Tagged 2.5D, 3D, Herb Reiter, IBM, Reiter, Three-dimensional integrated circuit, TSMC, Xilinx
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3D Thursday: The low down on low-power CPU-memory connections from EDPS
Earlier this month at EDPS, Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, said that Wide I/O SDRAM memory was going to drive the earliest adoption of 3D IC assembly techniques. Not simply because Wide I/O … Continue reading
Posted in 2.5D, 3D, EDA360, Memory, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O
Tagged SDRAM, SerDes, Wide I/O SDRAM
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3D Thursday: Is Wide I/O SDRAM free for the end user???
A recent email from Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, suggested that Wide I/O used in a 3D stack is free for the end user. In other words, there’s no incremental cost in the … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O
Tagged 3D, SDRAM, TSV, Wide I/O, Wide I/O SDRAM
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3D Thursday: CEA-Leti launches Open 3D IC assembly partnership program
ElectroIQ reports that CEA-Leti in Grenoble has just launched an Open 3D IC program to permit companies more open access to the 3D IC assembly technologies developed at the research center. Last December, CEA-Leti and ST-Ericsson made a joint presentation … Continue reading
Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O
Tagged 3D, 3D IC, CEA-Leti, micro pillar, microbump, ST Ericsson, TSV
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3D Thursday: Count Renesas in with the 3D IC poker game, says Nikkei Electronics
Last week, Masahide Kimura at Nikkei Electronics in Japan published an article titled “Renesas to Commercialize TSV Technology for Wide I/O DRAM-compatible Mobile SoCs” that clearly puts Renesas in the middle of the industry’s 3D IC efforts. Reading between the … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O
Tagged JEDEC, mobile phone, Renesas, SoC, Wide I/O
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3D Week: JEDEC Wide I/O Memory spec cleared for use
According to Ken Shoemaker, Vice-Chair of the JEDEC 42.6 Low Power Memories committee, the Wide I/O specification has been finalized and approved by the directors. It will be published shortly. Participants in the effort included representatives from Elpida, Hynix, Micron, … Continue reading
Posted in EDA360, SoC Realization, System Realization, Wide I/O
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