First, Jack broke needed a way to measure just the microcontroller power consumption on the Hitex eval board he used for tests. He did this by adding a 5-ohm resistor in series with the microcontroller’s ground lead and then measuring the voltage drop across the resistor.

Then he wrote a series of tests to exercise the two processors. The processors take turns running these tests and a couple of GPIO pins go high or low to indicate which processor is operating. This 3-trace scope image shows you what the output of the test setup looks like.

The yellow trace shows the active periods for the ARM Cortex-M4 processor core. The Green trace shows the active periods for the ARM Cortex-M0 core. Note that it takes the ARM Cortex-M0 core a lot longer to run the same code, as you’d expect.

The blue trace shows the voltage across the 5-ohm resistor, which is proportional to the amount of current flowing through the NXP dual-core microcontroller. As you’d expect, the chip draws much less power when the ARM Cortex-M0 core is running and the ARM Cortex-M4 core is sleeping than vice versa.

The ARM Cortex-M4 with its SIMD and floating-point capabilities ran the tests 12 to 174 times faster than the ARM Cortex-M0 core and consumed 2x to 9x more power. Consequently, the ARM Cortex-M4 core proved to be more energy efficient than the ARM Cortex-M0 core.

This series of tests demonstrates that you can often get more energy efficiency from a fast processor core that sleeps a lot instead of a slower processor core that draws less power while running all or most of the time. Yet another example of how system-level considerations come into play when developing a low-power or low-energy design.

(Many thanks to my good friend Jack Ganssle for permission to reprint his results.)

Let’s say you need a really small exploration vehicle to check out the ruins of a natural disaster to search for survivors. Nature has been at this design task for millions of years and has produced an optimized design otherwise known as the hissing cockroach. Unfortunately, we’re not very good at controlling hissing cockroaches, either individually or in large populations. Well, Tahmid Latif and Alper Bozkurt at the Integrated Bionic Microsystems Laboratory (iBionicS Lab) at North Carolina State University have developed a strap-on control system that turns a hissing cockroach into a driveable robotic device.

The backpack drives a couple of stimulation electrodes that are attached to the stubs of the cockroach’s amputated antennae. These electrodes allow a driver to steer the cockroach, as exhibited in a pretty interesting video.

For a proof of concept, the researchers used a Microchip PIC 16F630 microcontroller with an IA4320 ISM band FSK receiver that took commands from a commercial radio-control transmitter. It worked, but the prototype controller was too heavy and handicapped the mobility of the cockroach. So the researchers developed a lighter system based on a Texas Instruments CC2530 Zigbee-based SoC.

You can read all about it in the paper: “Line Following Terrestrial Insect Biobots” presented at the 34th International Conference of the IEEE Engineering in Medicine and Biology Society held in San Diego, CA a couple of weeks ago.

Note: The Cadence Allegro and OrCAD pcb design tools support IPC-2581. Cadence is a founding member of the IPC-2581 Consortium and believes it’s in the industry’s best interest that an open, public, neutrally maintained standard be adopted by all segments of the PCB design, fabrication, assembly, and test supply-chain.

For more information on IPC-2581, see Richard Goering’s blog post “IPC-2581 Update: Forward Progress on a PCB Data Transfer Standard.”

MIPI Interface Block Diagram for Mobile Devices

If you look at the diagram, you might see a glaring omission as I did. There’s no MIPI standard for connecting large amounts of RAM to the host application processor. To date, LPDDR standards have done this job and may continue to do so in the future. The addition of a PCIe protocol on top of the existing M-PHY physical layer presents another interesting possibility for a low-power interconnect spec. The MIPI Alliance’s M-PHY started as a 1.25Gbits/sec physical-layer interface and will reportedly hit 5.8Gbits/sec with a third-generation spec expected to appear next year.

There are several important sessions at this conference including:

• “A Multi-Die Integration Strategies Session” led by Pat Tang of STATSChipPAC.
• A session on “Enabling Multi Die Integration” led by Kumar Nagarajan of Xilinx
• A session on “Emerging Technologies for Multi-Die Packaging” led by John Xie of Altera
• A panel on “Drivers for Multi-Die Packaging” led by Ivor Barber of LSI Corp and Rich Rice of ASE

The keynote by Anwar Mohammed of Huawei Technologies looks to be just as interesting: “The Promises and Pitfalls of 2.5D Packaging…A User Perspective.”

That’s a lot for one day.

Registration for MEPTEC members is $475 and it’s $575 for non-members.

More info here.

Registration is here.

Rampon is a Partnership Marketing Specialist at ARM.

Seriously.

More info and registration here.

For more information on the Freescale Kinetis L series microcontrollers, see:

How low can you go? ARM does the limbo with Cortex-M0+ processor core. Tiny. Ultra-low-power.

Freescale demonstrates first-pass Kinetis L silicon at Design West

Freescale starts sampling $0.49 Kinetis L microcontrollers based on ARM Cortex-M0+ processor core