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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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2.5D 3D 20nm 28nm Altera Analog Android Apple ARM ARM architecture ASIC Cadence Cortex-A15 Cortex-M0 DAC Dave Jones EDA EDPS FinFET Flash FPGA Freescale Freescale Semiconductor GlobalFoundries IBM Intel iPhone Jim Hogan Linux Low Power microcontroller Micron Microsoft Mixed Signal Nvidia Qualcomm Samsung SDRAM SoC STMicroelectronics Texas Instruments TSMC USB verification XilinxTop Posts
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Want a peek at a possible Qualcomm 3D IC roadmap?
- Friday Video: Webcam + Open-source video code + Arduino Uno microcontroller board + pan/tilt servo make automated face-tracker, prove the power of an apps-centric world
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- How Skyera developed the 44Tbyte, enterprise-class Skyhawk SSD from the ground up. A System Realization story.
- The DDR4 SDRAM spec and SoC design. What do we know now?
- Agilent knocks one out of the park with new, low-cost line of digital scopes—a very competitive entry into the low-end DSO market and a perfect example of EDA360 design using end-to-end design and apps.
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)
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Tag Archives: 3D
3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work
I recently covered the groundbreaking WIOMING 3D chip design done by CEA-Imec in conjunction with ST-Ericsson. (See “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. … Continue reading
3D Thursday: Boosting the bandwidth of Wide I/O SDRAM to 1 Tbit/sec through standards evolution
This week’s DesignCon included a panel on 3D standards. You can read a review of the panel here in EETimes. Many topics were discussed, but the nugget I want to focus on in this blog post is the issue of … Continue reading
Posted in System Realization, EDA360, SoC Realization, Silicon Realization, 3D, SoC, 2.5D
Tagged 3D, 2.5D, SDRAM, JEDEC, Wide I/O
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3D Thursday: CEA-Leti launches Open 3D IC assembly partnership program
ElectroIQ reports that CEA-Leti in Grenoble has just launched an Open 3D IC program to permit companies more open access to the 3D IC assembly technologies developed at the research center. Last December, CEA-Leti and ST-Ericsson made a joint presentation … Continue reading
Posted in System Realization, EDA360, SoC Realization, Silicon Realization, 3D, SoC, 2.5D, Wide I/O
Tagged 3D, ST Ericsson, 3D IC, TSV, CEA-Leti, microbump, micro pillar
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3D Thursday: SEMATECH wades in to develop assessment criteria for 3D manufacturing equipment and processes
Earlier this week, SEMATECH—the global semiconductor industry’s research consortium—announced that it plans to conduct “Equipment Maturity Assessments (EMAs) of several critical 3D tools during 2012 to establish functional equipment capabilities and address high-volume manufacturing maturity issues” through its wholly owned … Continue reading
Posted in 2.5D, 3D, EDA360, SoC, SoC Realization, System Realization
Tagged 2.5D, 3D, Sematech
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3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it?
For the last 3D Thursday blog post of 2011in the EDA360 Insider, I thought I’d take a flight of fancy and try to put as many of this year’s 3D IC concepts as possible together to see what we might … Continue reading
Posted in System Realization, EDA360, SoC Realization, 3D, Memory, SoC, 2.5D
Tagged IBM, Micron, 3D, 2.5D, JEDEC, HMC, Wide I/O
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3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
Yesterday, at the RTI 3D Conference, Pascal Vivet from CEA-Leti and Vincent Guérin from ST-Ericsson unveiled a 3D IC project that represents a real Tour de Force of cutting-edge system technology. The quest starts with a key question: “What’s the … Continue reading
Posted in 3D, ARM, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 3D, Cadence, Leti, LTE, Multicore, NoC, ST Ericsson, TSV, Wide I/O
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3D Week: The three interconnect crises of the electronics industry and the inevitability of 3D. Believable?
Many people in the electronics industry view 3D IC assembly as not being in the mainstream. That’s easy to understand. It’s not at the moment. Yet I do believe in the inevitability of 3D assembly. Here’s why. At last week’s … Continue reading
Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 2.5D, 3D, IC, packaging
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3D Thursday (OK, Friday): Live from Newport Beach—The IEEE 3D IC Workshop
I’m attending the all-day workshop on 3D ICs being held by the local IEEE Chapter of the CPMT (Components, Packaging, and Manufacturing Technology) Society and it’s a huge success with 150 attendees. I’m busy listening to presentations, but here’s a … Continue reading
3D Thursday: A busy week coming up for 3D ICs
This is a very busy week for 3D in the world of the EDA360 Insider. I am about to board a plane for John Wayne Airport to attend an IEEE workshop on 3D IC assembly. Next Monday, there’s a meeting on … Continue reading
Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 3D, 3D IC
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3D Thursday: Is 2.5D IC assembly “buzz-worthy”?
I’ve written several times about the Xilinx Virtex-7 2000T FPGA that uses 2.5D IC assembly techniques to form four FPGA die into one FPGA package with two million logic cells. (See “3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers … Continue reading
Posted in 2.5D, 3D, Silicon Realization, SoC, SoC Realization
Tagged 2.5D, 2000T, 3D, Virtex 7, Xilinx
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3D Thursday: Who is responsible for successful 2.5D and 3D assembly? eSilicon is perhaps saying “Us”
Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: … Continue reading
Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization
Tagged 2.5D, 3D, sSilicon, Xilinx
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3D Thursday: Where can you start with 3D?
My first panelist to speak on last week’s 3D IC panel at the 9th International SoC Conference in Newport Beach was Herb Reiter, generally known as “Mr. 3D.” Herb knows everyone in the industry connected to anything 3D. He’s been … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC Realization, System Realization
Tagged 3D, 3D IC, GSA, Sematech, Xilinx
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3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)
Tuesday, Xilinx announced that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, … Continue reading
Posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 2.5D, 3D, Amkor, FPGA, TSMC, Virtex, Xilinx
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Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)
Xilinx announced today that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, … Continue reading
Posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, TSV
Tagged 2.5D, 3D, Amkor, FPGA, TSMC, Xilinx
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3D Thursday: Can IBM and 3M really build a 3D, 100-chip stairway to heaven with glue?
IBM and 3M have announced a program to develop heat-dissipating adhesives that would permit the construction of tall, 3D “towers” of silicon chips in 3D assemblies. The stated target: 100 stacked chips. Some things about 3D assembly are absolutely uncontroversial: … Continue reading
3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you’re not designing FPGAs!
Want an advanced course in low-power design alternatives for advanced-process SoC design? Xilinx wants you to have one… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC Realization
Tagged 2.5D, 3D, FPGA, Xilinx
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3D Thursday: 3D-IC Design Tools and Services Tour Guide is just in time for DAC. You can download a copy now.
The GSA has just issued a 3D-IC tools and services guide in time for DAC. This 62-page guide provides eight pages of background info on the state of 3D assembly technology based on public information like that provided by Xilinx … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC Realization, System Realization
Tagged 2.5D, 3D, FPGA, GSA, Virtex 7, Xilinx
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The 3D IC has landed: Dynamite panel of 4+1 3D experts at EDPS in Monterey next month. Sign up now!
I’ve been waiting to break this news and I finally can. The Electronic Design Process Symposium (EDPS) will host a 3D panel at next month’s event. Last year, I moderated a 3D panel at LSI Corp’s Technology Day in San … Continue reading
April 8 shaping up to be 3D day at EDPS. Register now before the registration increase!
With the presentations shaping up, Friday April 8 is shaping up to be 3D IC day at the Electronic Design Process Symposium (EDPS) being held in Monterey, California next month. Here’s the list of 3D presentations and panels: Biswadeep Chatterjee: … Continue reading
Stereoscopic 3D Computing: Free IEEE meeting March 8 in San Jose
Next week, on March 8, Cadence in San Jose will be hosting the Silicon Valley chapter of the IEEE Computer Society meeting and the topic is one of tremendous interest: 3D Stereoscopic Computing. The speaker is Sunil Jain, Lead Architect … Continue reading
New Cadence White Paper on 3D IC design with TSVs (through silicon vias). Are you ready for this? Are you sure?
Richard Goering’s blog “Whitepaper: 3D ICs Pose Design Challenges, But No ‘Showstoppers’” summarizes a new Cadence White Paper on 3D IC design. As Richard writes, “3D ICs with through-silicon vias (TSVs) promise tremendous power, cost, and size advantages, but they … Continue reading
Perplexed or puzzled about 3D ICs? Where are we now? Read this! Now!
R&D Magazine just published a really comprehensive review of the Semicon Taiwan 3D Forum. This is a quick read with a lot of great info starting with the major themes of the conference: Everyone has bought into the inevitability of … Continue reading
3D Conference next week in San Francisco, coming to a high-volume, high-performance product near you
There’s a low-profile, high-content 3D IC conference taking place next week adjacent to the San Francisco Airport in Burlingame, California. The event runs from December 8-10 and includes several sessions you’ll want to see if you’re at all connected to … Continue reading
The 3D SSD
You need three things from a solid-state disk (SSD): speed, capacity, and reliability. You need three things from a portable SSD: speed, capacity, reliability, and diminutive size. And you can’t get much smaller than packing an SSD into the form … Continue reading
Need really big FPGAs? Xilinx will be taking the “3D” route for initial Virtex 7 parts
Ivo Bolsens, the Xilinx CTO and Senior VP, presented a keynote at the 8th International SoC Conference a couple of weeks ago and one of the aspects of FPGA development that he discussed was Xilinx’ plan for creating large-capacity Virtex … Continue reading
