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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud2.5D 3D 20nm 28nm Altera Analog Android Apple ARM ARM architecture ASIC Cadence Cortex-A15 Cortex-M0 DAC Dave Jones EDA EDPS FinFET Flash FPGA Freescale Freescale Semiconductor GlobalFoundries IBM Intel iPhone Jim Hogan Linux Low Power microcontroller Micron Microsoft Mixed Signal Nvidia Qualcomm Samsung SDRAM SoC STMicroelectronics Texas Instruments TSMC USB verification Xilinx
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- Want a peek at a possible Qualcomm 3D IC roadmap?
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: Webcam + Open-source video code + Arduino Uno microcontroller board + pan/tilt servo make automated face-tracker, prove the power of an apps-centric world
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- The DDR4 SDRAM spec and SoC design. What do we know now?
- Agilent knocks one out of the park with new, low-cost line of digital scopes—a very competitive entry into the low-end DSO market and a perfect example of EDA360 design using end-to-end design and apps.
- How Skyera developed the 44Tbyte, enterprise-class Skyhawk SSD from the ground up. A System Realization story.
- 3D Thursday: Intel Penwell SoC for mobile phones employs POP (package-on-package) LPDDR2 SDRAM to reduce power
- 3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)
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Tag Archives: Cadence
A couple of days ago, I let you know that Cadence had just published a comprehensive book on mixed-signal SoC design and verification. The book’s title is the “Mixed-Signal Methodology Guide,” written by the top mixed-signal design experts from across … Continue reading
Daniel Nenni has just published a great, short overview of the specifications for the TSMC 20nm process technology on his SemiWiki site. Nenni’s report hits the important benefits of the advanced process technology right at the beginning: 30% faster 1.9x … Continue reading
Briefly noted: SemiWiki’s Paul McLellan has just published a short analysis of the 3D announcements made last week at DAC by TSMC and Cadence.
Yesterday, I wrote about a terrific discussion panel about the challenges of 20nm design at DAC. I am moderating the panel and there will be speakers from the Common Platform partners including IBM, Samsung, GLOBALFOUNDRIES (just confirmed!), and Cadence. (See … Continue reading
Layout Dependent Effects in Advanced Nodes: Boo! Are you scared yet? FREE DAC Seminar helps calm the nerves
You can change transistor threshold voltages on advanced-node designs just by placing them too near something else. (Scholarly paper with detailed analysis here.) You can solve this problem with overdesign but there are better ways. Layout-dependent effects and smart ways … Continue reading
The second of a series of three Cadence Webinars on 20nm design is now archived and available for viewing if you missed the live event. You can read about this Webinar in Richard Goering’s blog (“Cadence, Samsung Detail 20nm RTL-to-GDSII … Continue reading
Last week ARM, TSMC, and Cadence held a Webinar on 20nm design covering three main points: Its adoption is inevitable. The design and manufacturing challenges are significant. The challenges are manageable given the right tools and methodologies, and solutions are … Continue reading
What better way to understand the realities of 3D IC assembly than to listen to the pioneers who have already taken the arrows so you won’t have to? That’s the topic of the upcoming DAC panel: “Is 3-D Ready for … Continue reading
3D Thursday: Practical Approaches to 3-D IC—TSV/Silicon Interposer and Wide IO Implementation From People Who Have Been There, Done That
If you’re like me, you’ve heard more than enough theory about 3D IC assembly and you’re ready to get on with the main event and design something. Want to hear about 3D IC technology that works? Now? Then you will … Continue reading
Want to go see the latest EDA offerings on the DAC exhibit floor but you (or your boss) can’t spring for the cash? Bummer. Atrenta, Cadence, and Springsoft feel your pain and once more, the three amigos have partnered to … Continue reading
With the 20nm click on the process technology dial staring us in the face, you might be wanting some informative, experience-based help. Three free Webinars taking place on May 1, 2, and 3 will give you some extra oomph in … Continue reading
Last Friday, I moderated an all-star, hand-picked 3D-IC panel at the Electronic Design Process Symposium (EDPS) in Monterey, California. The panel included: Phil Marcoux, Managing Director, PPM Associates, experienced packaging expert Herb Reiter, President of eda2asic, Chair of the Global … Continue reading
Friday Video: Two of this week’s EETimes ACE Award Winners related to each other: Xilinx Zynq and Cadence Virtual System Platform
This week at Design West in San Jose—the conference formerly known as the Embedded Systems Conference—EETimes gave out ACE awards to the year’s outstanding companies, people, and products. Two of the ACE winners have something in common. The first winner, … Continue reading
Use of IP in the design of SoCs has long been a fact. The very name “SoC” says that you’re using microprocessor IP at the very least. With that comes memory IP, memory controller IP, interface IP, analog IP, etc. … Continue reading
Want to know what’s going to happen at 20nm, 14nm, and beyond? A few answers from Frank Leu of Cadence
Last week at the Global Technology Forum held at the Santa Clara Convention Center in Silicon Valley, Cadence VP of R&D Frank Leu discussed the things we’ve learned about 20nm IC manufacturing, what we are learning about 14nm, and where … Continue reading
On leap day (Feb 29), EDAC held its annual CEO Forecast and Industry Vision event at Silicon Valley Bank in, er, Silicon Valley. Speakers included CEOs Wally Rhines (Mentor), Aart de Geus (Synopsys), Lip-Bu Tan (Cadence), and Ed Cheng (Gradient) … Continue reading
This week at CDNLive!, Cadence President and CEO Lip-Bu Tan used a video from GoPro in his keynote speech. (For a summary of this speech, see “CDNLive! – Lip-Bu Tan Keynote Cites Semiconductor Growth Drivers” by Richard Goering.) In case … Continue reading
Rick Cassidy, president of TSMC North America, gave a keynote speech at CDNLive! Silicon Valley this week and discussed 3D IC assembly in the context of Moore’s Law. “I think we can actually beat Moore,” he said after discussing planar … Continue reading
EDPS (April 5-6) in Monterey tackles “Top EDA Problems” with speakers from Broadcom, Cadence, AMD, and Synopsys
Early next month in Monterey, California, the Electronic Design Processes Symposium will take on the “Top Five EDA Problems.” For the purpose of this event, these problems would appear to be DFT (design for testability), System-Level EDA, Parallel EDA, and … Continue reading
Last week at DVCon, Cadence sponsored a low-power-themed lunch with the promise “Earn Your Degree in the Low-Power Arts and Sciences.” The panel consisted of: Qi Wang, technical marketing group director, Cadence Ruggero Castagnetti, distinguished engineer, LSI Corp. Sushma Honnavara … Continue reading
Richard Goering has written up last week’s EDA CEO panel, sponsored by EDAC (the EDA Consortium). The panel took place at the Silicon Valley Bank’s headquarters in Santa Clara, California and featured CEOs from four EDA companies—Cadence (Lip-Bu Tan), Gradient … Continue reading
As part of this week’s DVCon event being held in Silicon Valley, the EDAC Emerging Companies Committee sponsored a really intense and well-attended evening panel on hardware/software codesign. The effervescent Paul McLellan moderated the panel. (If you’ve not read his book, … Continue reading
3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
Yesterday, at the RTI 3D Conference, Pascal Vivet from CEA-Leti and Vincent Guérin from ST-Ericsson unveiled a 3D IC project that represents a real Tour de Force of cutting-edge system technology. The quest starts with a key question: “What’s the … Continue reading
My second panelist to speak on last week’s 3D IC panel at the 9th International SoC Conference in Newport Beach was Samta Bonsal who manages Silicon Realization Strategic Marketing at Cadence Design Systems. Samta has two hats at Cadence. One … Continue reading
Atrenta announced this week just before ARM TechCon 2011 that it has joined the Cadence System Realization Alliance. The first result of this agreement is to ensure seamless operation of the Atrenta Spyglass platform with the Cadence C-to-Silicon Compiler. Atrenta … Continue reading