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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- Nvidia Tegra 3 based on five ARM Cortex-A9 cores is mobile processor of the year declares Microprocessor Report
- Xilinx Zynq EPPs based on two ARM Cortex-A9s create a new category that fits in among SoCs, FPGAs, and microcontrollers
- Raspberry Pi + Canon = Camera Pi: ARM 11 and Linux hack of a Canon 5D Mk II DSLR
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- Freescale starts sampling $0.49 Kinetis L microcontrollers based on ARM Cortex-M0+ processor core
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?
- Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu
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Tag Archives: CPF
Low-Power Design: Is the Problem Solved?
“Once upon a time, you would complain if your cell phone didn’t work on one [battery] charge,” said Qi Wang—Cadence Technical Marketing Group Director for Low-Power Solutions—during his EDPS presentation in Monterey last week. “After Apple introduced the iPhone, your … Continue reading
Posted in EDA360, IP, Low Power, Silicon Realization, SoC, SoC Realization, System Realization
Tagged CPF, Low Power, PSOC, RTL, SoC
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Power-intent methodologies: Can’t we all just get along?
All ASIC and SoC designs are low-power designs at or below the 45nm node. For that reason alone, the industry has seen the rise of power-intent descriptions to help SoC and Silicon Realization teams develop new chip designs. For the … Continue reading
Posted in EDA360, Low Power, Silicon Realization, SoC, SoC Realization
Tagged ASIC, CPF, IEEE 1801, Silicon Realization, SoC, System-on-a-chip, UPF
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