Search EDA360 Insider
Hey!!! Subscribe now to the EDA360 Insider!
-
Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud
2.5D 3D 20nm 28nm Altera Analog Android Apple ARM ARM architecture ASIC Cadence Cortex-A15 Cortex-M0 DAC Dave Jones EDA EDPS FinFET Flash FPGA Freescale Freescale Semiconductor GlobalFoundries IBM Intel iPhone Jim Hogan Linux Low Power microcontroller Micron Microsoft Mixed Signal Nvidia Qualcomm Samsung SDRAM SoC STMicroelectronics Texas Instruments TSMC USB verification XilinxTop Posts
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- Nvidia Tegra 3 based on five ARM Cortex-A9 cores is mobile processor of the year declares Microprocessor Report
- Friday Video: Webcam + Open-source video code + Arduino Uno microcontroller board + pan/tilt servo make automated face-tracker, prove the power of an apps-centric world
- Friday Video: Two more low-cost, ARM-based, embedded-Linux development boards from ODROID and Google
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- Raspberry Pi + Canon = Camera Pi: ARM 11 and Linux hack of a Canon 5D Mk II DSLR
- 3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet
- Today’s Apple iPhone 4S intro emphasizes apps. Built-in apps
- Collaboration is key to making DFM work at 28nm and below
- 3D Thursday: Micron to present Hybrid Memory Cube status at EDPS in Monterey, April 6—there’s a lot of news
Download the EDA360 Vision Paper here:
Tag Archives: GDDR5
Zowie! More than 50 x86 cores on the Intel Knights Corner Manycore Coprocessor
Today at the Hot Chips 24 conference, George Chrysos discussed the Intel MIC (Many Integrated Core) architecture of the Knights Bridge chip, to be formally called the Intel Xeon Phi coprocessor. This chip runs Linux, but it’s designed to act … Continue reading
Posted in EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged GDDR5, Intel, Knights Bridge, Manycore, Phi, Xeon
2 Comments
What would you do with a 23,000-simultaneous-thread school of piranha?…asks NVIDIA
Last night, Michael Shebanow took members of the local IEEE Computer Society deep into the world of graphics processing and graphics processing units (GPUs). Over an hour and a half, he revealed some interesting and surprising facets to the topic. … Continue reading
Posted in EDA360, Silicon Realization, SoC Realization, System Realization
Tagged AMD, DDR, Fermi, GDDR5, Nvidia
Leave a comment
