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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud2.5D 3D 20nm 28nm Altera Analog Android Apple ARM ARM architecture ASIC Cadence Cortex-A15 Cortex-M0 DAC Dave Jones EDA EDPS FinFET Flash FPGA Freescale Freescale Semiconductor GlobalFoundries IBM Intel iPhone Jim Hogan Linux Low Power microcontroller Micron Microsoft Mixed Signal Nvidia Qualcomm Samsung SDRAM SoC STMicroelectronics Texas Instruments TSMC USB verification Xilinx
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- Nvidia Tegra 3 based on five ARM Cortex-A9 cores is mobile processor of the year declares Microprocessor Report
- Friday Video: Webcam + Open-source video code + Arduino Uno microcontroller board + pan/tilt servo make automated face-tracker, prove the power of an apps-centric world
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- Friday Video: Two more low-cost, ARM-based, embedded-Linux development boards from ODROID and Google
- Collaboration is key to making DFM work at 28nm and below
- 3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet
- TI Stellaris LaunchPad eval board features ARM Cortex-M4F. Intro price: $4.99. Get yours now.
- Friday Video: Multi-core ARM CubeStormer II solves Rubik’s Cube in 8 seconds from punching the start button to solved puzzle!
- 3D Thursday: Micron to present Hybrid Memory Cube status at EDPS in Monterey, April 6—there’s a lot of news
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Tag Archives: JEDEC
Want to know why you need to be at Memcon this year? Here’s Denali Software founder Sanjay Srivastava to tell you why: Now go and sign up! It’s a free ticket and includes breakfast, lunch, and some goodies—not to mention … Continue reading
Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading
Today’s GSA Silicon Summit held at the Computer History Museum in Mountain View, California included a talk on 3D IC assembly by Nick Yu, VP of Engineering, VLSI Engineering, at Qualcomm. Yu is in charge of Qualcomm’s technology roadmaps including … Continue reading
This week’s DesignCon included a panel on 3D standards. You can read a review of the panel here in EETimes. Many topics were discussed, but the nugget I want to focus on in this blog post is the issue of … Continue reading
Last week, Masahide Kimura at Nikkei Electronics in Japan published an article titled “Renesas to Commercialize TSV Technology for Wide I/O DRAM-compatible Mobile SoCs” that clearly puts Renesas in the middle of the industry’s 3D IC efforts. Reading between the … Continue reading
3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it?
For the last 3D Thursday blog post of 2011in the EDA360 Insider, I thought I’d take a flight of fancy and try to put as many of this year’s 3D IC concepts as possible together to see what we might … Continue reading
Although DDR3 memory is just ramping up in sales, JEDEC has been working on the next-generation DDR4 specification for faster SDRAM that consumes even less power. To achieve these goals, JEDEC announced yesterday that has specified the following key features … Continue reading
DDR4 SDRAM is coming. JEDEC may not have released the final spec yet but Samsung made the first DDR4 memory chip announcement in January of this year—a 2133MHz device built with a 30nm process technology—and Hynix followed suit in April … Continue reading
Urgent: You have only 24 hours to sign up for a free DDR4 Webinar including just-released info from the JEDEC committee
I just heard from the Cadence memory interface guru himself, Marc Greenberg, about a DDR4 Webinar he’s giving tomorrow (Thursday) during the EETimes Virtual SoC event. Here’s what Marc wrote: “I am presenting a Webinar on DDR4 tomorrow (Thursday) at … Continue reading