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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud2.5D 3D 20nm 28nm Altera Analog Android Apple ARM ARM architecture ASIC Cadence Cortex-A15 Cortex-M0 DAC Dave Jones EDA EDPS FinFET Flash FPGA Freescale Freescale Semiconductor GlobalFoundries IBM Intel iPhone Jim Hogan Linux Low Power microcontroller Micron Microsoft Mixed Signal Nvidia Qualcomm Samsung SDRAM SoC STMicroelectronics Texas Instruments TSMC USB verification Xilinx
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- Nvidia Tegra 3 based on five ARM Cortex-A9 cores is mobile processor of the year declares Microprocessor Report
- Friday Video: Webcam + Open-source video code + Arduino Uno microcontroller board + pan/tilt servo make automated face-tracker, prove the power of an apps-centric world
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- Friday Video: Two more low-cost, ARM-based, embedded-Linux development boards from ODROID and Google
- Collaboration is key to making DFM work at 28nm and below
- 3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- 3D Thursday: Micron to present Hybrid Memory Cube status at EDPS in Monterey, April 6—there’s a lot of news
- TI Stellaris LaunchPad eval board features ARM Cortex-M4F. Intro price: $4.99. Get yours now.
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Tag Archives: Mentor Graphics
Use of IP in the design of SoCs has long been a fact. The very name “SoC” says that you’re using microprocessor IP at the very least. With that comes memory IP, memory controller IP, interface IP, analog IP, etc. … Continue reading
Last week at DVCon, Cadence sponsored a low-power-themed lunch with the promise “Earn Your Degree in the Low-Power Arts and Sciences.” The panel consisted of: Qi Wang, technical marketing group director, Cadence Ruggero Castagnetti, distinguished engineer, LSI Corp. Sushma Honnavara … Continue reading
Richard Goering has written up last week’s EDA CEO panel, sponsored by EDAC (the EDA Consortium). The panel took place at the Silicon Valley Bank’s headquarters in Santa Clara, California and featured CEOs from four EDA companies—Cadence (Lip-Bu Tan), Gradient … Continue reading