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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- 3D Thursday: A look at some genuine 3D NAND cells, courtesy of Micron
- Freescale starts sampling $0.49 Kinetis L microcontrollers based on ARM Cortex-M0+ processor core
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- Friday Video: Circuit simulation app for Android. SPICE for $10, runs in your hand? Well, almost.
- 3D Thursday: Power is a killer app for TI’s PowerStack 3D packaging—parasitics vanish
- Nvidia Tegra 3 based on five ARM Cortex-A9 cores is mobile processor of the year declares Microprocessor Report
- The DDR4 SDRAM spec and SoC design. What do we know now?
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Free Webinar teaches you how to mix C, C++, SystemC, and SystemVerilog verification models within UVM—October 20
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Tag Archives: optimization
Another blog entry about getting all of the performance you purchased from your EDA tools
Back in September, I wrote a blog entry titled “10 ways to get your EDA tools to run faster, smoother, and longer” based on an interview with Peter Vincent, who is with the Cadence EDA Infrastructure Acceleration Services team. Richard … Continue reading
