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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
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- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- Friday Video: Webcam + Open-source video code + Arduino Uno microcontroller board + pan/tilt servo make automated face-tracker, prove the power of an apps-centric world
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- Xilinx Zynq EPPs based on two ARM Cortex-A9s create a new category that fits in among SoCs, FPGAs, and microcontrollers
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Nvidia Tegra 3 based on five ARM Cortex-A9 cores is mobile processor of the year declares Microprocessor Report
- Raspberry Pi + Canon = Camera Pi: ARM 11 and Linux hack of a Canon 5D Mk II DSLR
- Friday Video: Learn the fundamentals of PCB design in 47 minutes, and enjoy it
- Itching to try out the Xilinx Zynq-7000 EPP? Ask your doctor if Zedboard is right for you
- The other shoe drops: Altera introduces SoC FPGA, mates ARM Cortex-A9 dual-core processor complex with FPGA fabric
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Tag Archives: PCIe
Less than two days left to sign up for free PCIe and NVMe verification training Webinar from Cadence
On June 25, Cadence and EETimes Education and Training are sponsoring a training Webinar covering verification flows for SoC designs with PCIe and/or NVMe interfaces. The Webinar will cover: Verification pitfalls of the PCIe and NVMe interface protocols Best practices … Continue reading
Posted in System Realization, EDA360, SoC Realization, Verification, VIP
Tagged Webinar, verification, PCIe, VIP, NVMe
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AMD’s new Trinity APU (Accelerated Processing Unit) for laptops/notebooks is a poster child for IP-centric SoC design
Yesterday, AMD introduced its second generation of A-series APUs (Accelerated Processing Units) that combine two to four Piledriver x86 microprocessor cores—each with 2Mbytes of L2 cache memory—with a Radeon 7000 GPU (Graphics Processing Unit), an HD Media Accelerator, a display … Continue reading
Posted in EDA360, SoC Realization, Silicon Realization, SoC, 32nm
Tagged DDR3, AMD, PCI Express, Advanced Micro Devices, PCIe, GPU, Radeon, APU
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Detailed analysis of the Cadence PCIe Gen 3 IP and VIP launch from SemiWiki’s Eric Esteve
A bit of analysis and a little history goes a long way to fleshing out the product announcement of Cadence’s PCIe Gen 3 IP and VIP offerings. This just-published analysis by SemiWiki’s Eric Esteve provides both.
Posted in EDA360, IP, SoC Realization, Verification
Tagged PCIe, PCIe Gen 3, PCIe Gen3
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