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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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2.5D 3D 20nm 28nm Altera Analog Android Apple ARM ARM architecture ASIC Cadence Cortex-A15 Cortex-M0 DAC Dave Jones EDA EDPS FinFET Flash FPGA Freescale Freescale Semiconductor GlobalFoundries IBM Intel iPhone Jim Hogan Linux Low Power microcontroller Micron Microsoft Mixed Signal Nvidia Qualcomm Samsung SDRAM SoC STMicroelectronics Texas Instruments TSMC USB verification XilinxTop Posts
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: Webcam + Open-source video code + Arduino Uno microcontroller board + pan/tilt servo make automated face-tracker, prove the power of an apps-centric world
- Want a peek at a possible Qualcomm 3D IC roadmap?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- Nvidia Tegra 3 based on five ARM Cortex-A9 cores is mobile processor of the year declares Microprocessor Report
- How Skyera developed the 44Tbyte, enterprise-class Skyhawk SSD from the ground up. A System Realization story.
- Two more low-cost dev boards based on the ARM Cortex-M4 with 1Mbyte of Flash, 192Kbytes of RAM: $15.57 and up
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
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Tag Archives: RTL
Xilinx Vivado Design Suite brings SoC design style to advanced-node FPGA development
In a complete overhaul of its FPGA design tools, Xilinx has just announced the Vivado Design Suite for its current-generation 7 Series FPGAs (including the Zynq-7000 Extensible Processing Platform) and future FPGA generations. With this design-tool release, Xilinx is acknowledging … Continue reading
Low-Power Design: Is the Problem Solved?
“Once upon a time, you would complain if your cell phone didn’t work on one [battery] charge,” said Qi Wang—Cadence Technical Marketing Group Director for Low-Power Solutions—during his EDPS presentation in Monterey last week. “After Apple introduced the iPhone, your … Continue reading
Posted in EDA360, IP, Low Power, Silicon Realization, SoC, SoC Realization, System Realization
Tagged CPF, Low Power, PSOC, RTL, SoC
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Software development for SoCs requires “bespoke” software enablement platforms
I’ve always wanted to use the British English word “bespoke” in a blog and Cadence Group Director of Product Marketing for the System Development Suite Frank Schirrmeister has now given me that opportunity with his EDPS forecast on system-level EDA … Continue reading
Posted in EDA360, System Realization
Tagged Android, FPGA, Google, iOS, iPad, iPhone, RTL, Software development kit
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EDPS (April 5-6) in Monterey tackles “Top EDA Problems” with speakers from Broadcom, Cadence, AMD, and Synopsys
Early next month in Monterey, California, the Electronic Design Processes Symposium will take on the “Top Five EDA Problems.” For the purpose of this event, these problems would appear to be DFT (design for testability), System-Level EDA, Parallel EDA, and … Continue reading
Posted in EDA360, Silicon Realization, SoC Realization, System Realization
Tagged AMD, Broadcom, Cadence, RTL, Synopsys
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System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang
Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading
