Search EDA360 Insider
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud2.5D 3D 20nm 28nm Altera Analog Android Apple ARM ARM architecture ASIC Cadence Cortex-A15 Cortex-M0 DAC Dave Jones EDA EDPS FinFET Flash FPGA Freescale Freescale Semiconductor GlobalFoundries IBM Intel iPhone Jim Hogan Linux Low Power microcontroller Micron Microsoft Mixed Signal Nvidia Qualcomm Samsung SDRAM SoC STMicroelectronics Texas Instruments TSMC USB verification Xilinx
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- Friday Video: Two more low-cost, ARM-based, embedded-Linux development boards from ODROID and Google
- Nvidia Tegra 3 based on five ARM Cortex-A9 cores is mobile processor of the year declares Microprocessor Report
- 3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- Collaboration is key to making DFM work at 28nm and below
- Go for the GHz? 8-core, Bulldozer-based AMD FX processor hits 8.429 GHz using liquid nitrogen and liquid helium!
- Xilinx 28nm low-power SoC design class, part 2: Process Technology
- Itching to try out the Xilinx Zynq-7000 EPP? Ask your doctor if Zedboard is right for you
- Friday Video: Dave Jones tears down a Zoom H1 audio recorder. You learn more about system design.
Download the EDA360 Vision Paper here:
Tag Archives: UVM
Verification expert Kathleen Meade has authored a methodology for applying UVM runtime phases that appears in the second edition of the Cadence UVM Book. On December 7, Kathleen will present a free verification Webinar covering the following topics: Basics of … Continue reading
Free Webinar teaches you how to mix C, C++, SystemC, and SystemVerilog verification models within UVM—October 20
Our world is filled with mixed verification models and that fact isn’t going to change soon. If you would like to learn how to efficiently combine mixed verification models to work within the Accelera Universal Verification Methodology (UVM), then there’s … Continue reading
Adam Sherilog Sherer, the Cadence Incisive Product Management Director, just published a blog about his experience in calling on several existing customers to discuss UVM (The Universal Verification Methodology being developed under Accelera’s banner). (“We Want UVM 1.0! When Do … Continue reading