Tag Archives: Xilinx

3D Thursday: Hybrid Memory Cube—wide I/O only more so—gets an industry consortium

Back in August, I wrote about the 3D SDRAM assembly called the Micron Hybrid Memory Cube (HMC, see “Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?”) and I called it a … Continue reading

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The other shoe drops: Altera introduces SoC FPGA, mates ARM Cortex-A9 dual-core processor complex with FPGA fabric

It’s been more than a year and a half since Xilinx first started to talk publicly about the fusion of processors and FPGAs—a product now known as Zynq. It seemed inevitable that Altera would eventually counter with a competing product … Continue reading

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3D Thursday: Do dis-integrated circuits reside in a 3D future? Does anyone (besides me) remember Project Tinkertoy?

I recently ran into this unusual article written by Joe Fjelstad and published on the Global SMT & Packaging Web site. The article discusses the possibility of building hybrid chips using a brick-and-mortar approach as advocated by a joint paper … Continue reading

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Fire lasers! An EDA360, System Realization, and SoC Realization case study with military lasers, processors, and FPGAs

Robert S Grimes’ recently published development story is a good case study in System Realization and SoC Realization. Grimes developed a quad laser control system for a high-power military application and the article he’s published in EETimes—Designing with core-based high-density … Continue reading

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6-Part series of blog posts on 28nm low-power design

Over the past week, I’ve published a 6-part series of blog posts based on the Xilinx White Paper describing how the company developed the low-power aspects of its Series-7 FPGA families. The lessons apply to any team developing ASICs and … Continue reading

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Xilinx 28nm low-power SoC design class, part 6: Vccaux, the “other” power supply

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading

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Xilinx 28nm low-power SoC design class, part 5: Intelligent clock gating

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading

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Xilinx 28nm low-power SoC design class, part 4: Power gating RAMs

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading

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Xilinx 28nm low-power SoC design class, part 3: Optimizing the transistor mix

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading

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Xilinx 28nm low-power SoC design class, part 2: Process Technology

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading

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3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you’re not designing FPGAs!

Want an advanced course in low-power design alternatives for advanced-process SoC design? Xilinx wants you to have one… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let … Continue reading

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3D Thursday: 3D-IC Design Tools and Services Tour Guide is just in time for DAC. You can download a copy now.

The GSA has just issued a 3D-IC tools and services guide in time for DAC. This 62-page guide provides eight pages of background info on the state of 3D assembly technology based on public information like that provided by Xilinx … Continue reading

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3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?

Last November, I wrote a blog entry about Xilinx’ plan to use 2.5D assembly techniques to create large Virtex 7 FPGAs using tiled 28nm silicon with interposers. (See “Need really big FPGAs? Xilinx will be taking the “3D” route for … Continue reading

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Friday video (2fer): 28nm FPGA videos from Xilinx and Altera

Recently, Xilinx announced shipping early samples of its 28nm Kintex-7 FPGAs. Now 28nm is the current bleeding-edge process node for logic processes and it’s no small feat to start shipping parts—even early engineering samples—at this node. Here’s a video of … Continue reading

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Need really big FPGAs? Xilinx will be taking the “3D” route for initial Virtex 7 parts

Ivo Bolsens, the Xilinx CTO and Senior VP, presented a keynote at the 8th International SoC Conference a couple of weeks ago and one of the aspects of FPGA development that he discussed was Xilinx’ plan for creating large-capacity Virtex … Continue reading

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