Cadence will be holding this year’s CDNLive! Silicon Valley at the San Jose Fairmont on October 26. Unfortunately, registration hit capacity quickly, before I had a chance to blog the event. However, there’s a CDNLive! wait list and you can still register for that (see below). The first half day of CDNLive! includes general sessions and keynotes. After a networking lunch, the event splits into tracks aligned with the three pillars of the EDA360 vision: System Realization, SoC Realization, and Silicon Realization.
System Realization presentations include topics such as advanced system-level, low-power design techniques; transaction-based acceleration; and metric-driven verification. SoC Realization topics include SoC-level power optimization, OVM-based verification of analog IP and mixed-signal SoCs, and an interesting talk about resolving the IP-SoC Tower of Babel. A large number of presentations this year address topics in Silicon Realization including RTL power profiling for early analysis and power optimization, tips and pitfalls for the first-time OVM user, and automated self-checking mixed-signal verification using Specman-AMS. That’s just day one. Day two includes fourteen half-day “techtorials” covering a broad range of topics across all three Realizations.