EDA360 defines System Realization as the development of complete hardware/software platforms ready for applications development even before the chip is designed. Cadence offers many free Webinars—both live and archived—that you might find useful. Here are a few Webinars related to System Realization that may interest you:
(Sign up for one or more of these Webinars here)
- XtremeEDA: The Importance of a Complete Methodology for ESL
This Webinar looks at a few of the reasons why ESL adoption has been slow and then discusses why a new approach based on a holistic methodology is changing the adoption rate.
- CircuitSutra: Role of Standards in TLM Driven Design and Verification Methodology
Discusses several important SoC modeling standards (OSCI SystemC IEEE 1666, OSCI TLM 1.0, OSCI TLM 2.0, OSCI SystemC synthesizable subset draft, STARC TL guidelines, and the OCP-IP modeling kit ) and then describes how these standards propel TLM-driven design and verification methodology.
- Imperas: Breaking New Ground in Embedded Software Development
This Webinar tells you how to perform software functional verification by integrating Incisive SystemC simulation, Incisive Software Extensions, processor models from OVP, and software simulation and verification tools from Imperas.
- Calypto: Application of Sequential Analysis for ESL Methodology Adoption
Discusses how sequential analysis tools from Calypto play a key role in today’s new era of application-driven System Realization.
- TSMC Reference Flow 11: ESL Focus on TLM Design and Verification Methodology (Live on October 6, 2010)
Introduces the various levels of design abstraction, discusses stages of refinement, and tells you how to architect an advanced UVM verification environment that works through your entire design flow.
- Developing Software for ARM-Based Devices (Live on October 13, 2010)
Learn to use the latest development tools for ARM-based embedded and application software creation, debug, and functional co-verification.
- System Realization Services from Cadence (Live on October 20, 2010)
Highlights the many ways that customers are successfully harnessing new methodologies and technologies to design and verify systems.
- TSMC Reference Flow 11: ESL Focus on High-Level Synthesis (November 3, 2010)
Introduces the concepts of modeling for high-level synthesis and describes a repeatable approach to creating high-quality RTL designs that meet area, timing, and power constraints.
Sign up for one or more of these Webinars here.