LSI held a conference this week and was fortunate to have Aart de Geus, Chairman and CEO of Synopsys, present a morning keynote. His theme was “SMART Collaboration to Accelerate Innovation” and the ideas presented strongly resonate with the EDA360 vision for the future of the electronics industry. SMART products drive everything in de Geus’ presentation. “Every product in the next decade will be connected,” he said, and pervasive connectivity will supply large amounts of raw intelligence that SMART products can use to make intelligent judgements. For example, a SMART building can use internal building sensors, external weather sensors, and weather forecasts drawn from the Internet to make smarter HVAC decisions. In this scenario, de Geus’ SMART concept differs from raw intelligence. SMART devices will use common sense to guide their actions. “SMART products create systemic value,” he said.
Then de Geus turned his attention to the way that semiconductors play in the SMART products arena and tied the discussion to the economics of semiconductor production and design. The industry’s CAGR is slowly and exponentially decreasing due to its huge size. Large, mature industries simply cannot grow as quickly (percentage-wise) as they could when small. To keep things perking along at all will take substantial innovation. “The race is on for 32nm and 28nm design and production while the older nodes are being squeezed for cost,” he said. (At this point, de Geus noted LSI’s announcement that morning of a 28nm custom silicon platform.)
However, said de Geus, software is both the long pole in the tent and the real product differentiator, enabled by hardware designs. Then he went even further: “Hardware and software are intimately linked for SoC development.” Software now represents half of the development cycle, noted de Geus as he showed a chart of development times, development costs, and then the subsequent revenue climb of a successful product. Done sequentially, software development consumes half of your time to market.
“Software delays time to revenue when done sequentially with the hardware,” said de Geus. Given that situation, it makes a lot of sense to do whatever you can to develop hardware and software in parallel and as quickly as possible. To develop in parallel, said de Geus, you need hardware and software IP reuse (to cut development time by reducing the need for custom design and verification). “IP is a wonderful shortcut to abstraction.”
You also need system-level prototyping, encompassed by what Cadence calls System Realization. There are two types of system-level prototyping, said de Geus, virtual prototyping and FPGA-based prototyping. Both of these prototyping approaches will aid bright architects in developing efficient system-level architectures. In addition, de Geus envisions system-level development that’s largely driven by applications, another EDA360 tenet. “You only develop hardware to accelerate software where needed.” This part of de Geus’ presentation clearly envisions a system-level design approach that is applications-driven and largely dependent on an increasing number of embedded, on-chip processors that execute software from the application level on down. Only when there are no available processors to execute the code at the required performance level does the design team need to design custom hardware or—better yet—obtain hardware design IP that accelerates task execution to the required level of performance. Virtual prototyping is valuable especially when the prototype is executing code that’s written so that it need not be modified to run in the final hardware design. The virtual prototyping system should be able to run the prototype code at near-real-time speeds.
Virtual prototypes have several advantages over hardware prototypes, but perhaps the biggest advantage is the ability to deeply probe the running software, at greater depth and with more debugging insight than is possible with code running on a hardware prototype. FPGA-based prototyping has been available for years, said de Geus. It’s a very powerful approach for mimicking hardware systems but it remains very complex and expensive—so far.
Applications sit above the prototypes. One of the required paths to a successful product design is to optimize the applications by running them on the target systems—as virtual prototypes, FPGA-based prototypes, or even the actual hardware if available. (It rarely is.)
All of these prototyping approaches have value when they permit software development earlier in the overall System Realization cycle. “Synopsys will be focused on this going forward,” said de Geus, who then noted a number of recent Synopsys acquisitions around system-level development. “These acquisitions are puzzle pieces,” said de Geus, “to be resolved over the next decade.” However, de Geus doesn’t see Synopsys necessarily supplying all of the puzzle pieces. “Systemic collaboration will be one of the big differentiators for companies going forward,” he said.
Closer to EDA’s home turf, de Geus called for “clairvoyant” design tools that have the ability to look up and down the tool chain to avoid problems ahead. EDA360 envisions this type of design by giving EDA tools the ability to convey design intent up and down the tool chain. Another required feature is the ability to abstract design details at any given level so that other EDA tools in the chain get just the information they need to help converge the design quickly without the need for overly detailed analysis. Digging deeper, de Geus gave a couple of examples of such abilities: modern synthesis tools can already look into the place-and-route level (what Cadence calls “physically aware synthesis”), and modern place and route tools are already aware of design rules (what Cadence calls “variation- and manufacturing-aware design closure”). These tool insights facilitate rapid design closure and signoff. As EDA tools become increasingly clairvoyant, said de Geus, design uncertainly will “monotonically decrease.”
Next, de Geus spoke about semiconductor yield. “Yield,” he said, “is getting as close to the guard rail as possible without crashing.” EDA tools up and down the design chain will be increasingly concerned with yield because semiconductor yield controls the steepness of a product’s adoption ramp. Parts that yield poorly are more costly and less available, which stunts the product’s early growth rate. Conversely, sales ramp quickly for parts that yield well at the start of production. In the past, the foundries were mostly responsible for yield but “the foundries are pretty good” these days said de Geus. Now, the big knobs on yield are systemic issues with the design itself and with the generated mask set.
In summing up his talk, de Geus called for SMART partnering—where the system-level customer develops applications and then uses prototyping systems to debug and perfect the applications on target hardware (real, simulated, or emulated). He then put up charts showing just a few of the apps available for just one system platform. “The number of applications feeding systems is just tremendous,” he said and then noted that semiconductor suppliers were being asked to provide substantially more software with their SoCs. Semiconductor suppliers are, in turn, asking the EDA suppliers to help them meet these new requirements. “When your customers ask you to do more tasks, that’s a good thing,” he concluded.