It’s been shocking and exhilarating to see all of the 28nm process announcements lately. If you throw them all into a basket, you might get the idea that nothing could be simpler than throwing together a 28nm design with hundreds of millions of gates. A tag team consisting of JC Parker and Vishwas Rao set a standing-room-only audience straight about that topic at this week’s LSI 2010 Conference and Showcase. Their presentation was titled “MegaChip Design: Accelerated Closure of 100+ Million Gate Designs.” Parker is LSI’s Director of Design Implementation and Rao is a Senior Manager of Design Closure Methodology. With titles like those, and from the presentation, you can tell these two have seen their share of design challenges.
Parker pointed out that 28nm design rules give you 3000K gates/mm2. “That makes life more complicated,” he said. On top of the mere complexity of having that many gates, there are a range of additional technology challenges including strain effects, orientation effects, leakage, variability, and multiple signoff corners. There’s no “app” to build the next 28nm SoC quipped Parker.
Only three slides in, Parker projected a slide with a long, long list of challenges broken into the following groups: design complexity, technology challenges, success measurables, and ecosystem complexity. Under design challenges, he listed the following:
- >100M gates
- >1 Gbit of memory
- > 200 MHz SerDes
- > 400mm2 die
- Power management
He then veered into the success measurables used at LSI:
- Yield/defect density
- Test quality
- First time right
- Turnaround time
- Power (W/MHz)
- Die cost
- NRE costs
These factors, and probably more, all must be tracked to measure the success level of each project.
Yet there’s a further variable in the mix. You’d like to have a stable platform and a core tool flow for all 28nm designs, and you can create platforms and flows that will work about 95% of the time said Rao, taking over for Parker. However, you’ll also need to customize the flow to achieve desired results for the rest of the design. You always need to do that for new technologies like 28nm because the rules aren’t yet fully written. Eventually, as you gain experience with the requirements of the new process technology, the exceptions become part of the platform.
Rao then gave the example of bus routing. “EDA tools struggle with long or high-fanout, top-level routes” he said. It takes some intervention to optize the design of such routes. LSI’s approach is to provide guidance and scripted routing for critical, bussed nets. The procedure is:
- Identify critical nets during floor planning
- Inter-block routing with calculations
- Add and position buffers with routing directives
- Adjust with coordinate scaling
This sequence results in the insertion of buffers along long routes to optimize the signal speed across the route. It’s not yet an automated procedure.
Customization has a price, however. You need to balance the customization level with the need for design stability and predictability. In addition, you need to look both forward and backward in the design flow to make sure you’re satisfying the design intent (a basic EDA360 tenet). In addition, you want a design that’s manufacturable and a design that yields well. To get an SoC design like that, you need manufacturing- and yield-aware design tools.